1996 Midwest Symposium on Circuits and Systems
August 18-21, 1996
Sessions Monday, August 19
7:30 am - 6:00 pm Registration Desk Open - Scheman First Floor
Lobby
7:30 - 8:30 am Continental Breakfast - Scheman First Floor Lobby
MA1.1 8:30 - 9:30 Plenary Session - Scheman Benton Auditorium
Future Directions in Adaptive Signal Processing
Professor W. Kenneth Jenkins,Department of Electrical and Computer
Engineering,The Coordinated Science Laboratory, University of Illinois,
Urbana, Illinois, USA (see special guest speakers, page 67)
9:30 - 10:00 Refreshment Break - Scheman First Floor Lobby
10:00 - 12:00 Concurrent Sessions
MA2.1 Analog Integrated Circuits I - M. Farooq, Chairperson
- Scheman Room 167
A Novel Slew-Rate Enhancement Technique for One-Stage Operational
Amplifers
Jaime Ramirez-Angulo, New Mexico State University, Las Cruces, New Mexico,
USA
A new and simple technique to enhance slew-rate in one-stage operational
amplifers is presented and verified experimentally. The technique requires
only two additional transistors and besides slew rate it results in improved
bandwidth and noise characteristics. These improvements are at the expense
of only slight increase in the static power dissipation of the operational
amplifer.
A Low-Input Resistance Class AB CMOS Current-Conveyor
Omid Oliaei, Patrick Loumeau, Ecole Nationale Supérieure des Télécommunications,
Paris, France
A basis for current-mode class AB operation in CMOS circuits is presented
and the linear behavior of class AB current-mode circuits is discussed.
A CMOS class AB current-conveyor designed by refering to the presented principle
is proposed. This current-conveyor offers a low input resistance for a small
bias current which makes it suitable for low-consumption designs.
CMOS Analog Cells for Low-Voltage VLSI Signal Processing Applications
Chung-Chih Hung, The Ohio State University, Columbus, Ohio, USA; Kari
Halonen, Veikko Porra, Helsinki University of Technology, Espoo, Finland;
Mohammed Ismail, The Ohio State University, Columbus, Ohio, USA
This paper presents two CMOS analog signal processing circuits which could
find wide use in low -voltage VLSI applications. The two circuits include
a voltage-to-current converter (V-I converter) and a multiplier. Both of
the circuits can operate from rail to rail with a power supply of 3V. They
were fabricated in a 2\mu m N-well double-poly CMOS process by MOSIS. In
either of the circuits, an N-type circuit cell is connected in parallel
with its P-type counterpart to achieve common-mode rail-to-rail operation.
Two Twin T Based Op Amp Oscillators Modified for Chaos
Ahmed S. Elwakil, Ahamed M. Soliman, Cairo University, Giza, Egypt
Two Twin T based op amp oscillators are modified for chaos using a single
nonlinear element, namely a JFET operating as a voltage controlled resistor.
The observed chaotic attractor persists for a wide and continuous range
of parameter values and different device types. The two autonomous circuits
have the interesting feature of a movable chaotic frequency spectrum from
the Hz band up to the Mhz band by simple parameter scaling. Spice simulation
results confirm chaoticity of both circuits.
MA2.2 Testing Methodologies - Mark Manwaring, Chairperson - Scheman
Room 262
Analysis and Detection of Faults in Emitter Coupled Logic (ECL) Devices
Sankaran M. Menon, South Dakota School of Mines and Technology, Rapid
City, South Dakota, USA
Bipolar Emitter Coupled Logic (ECL) devices can be fabricated at very high
densities and much lower power consumption. Faulty behavior in ECL devices
under various faults are investigated. Analysis of faulty behavior in ECL
devices exhibit stuck-at behavior and loss of complementarity. Delay faults
as well as enhanced power supply current are also observed in ECL devices.
A fault in ECL device manifesting as delay fault and exhibiting enhanced
power supply current is shown. Detection of the above behavior under faults
using logic monitoring requires careful and systematic generation of input
vectors. Testing for delay faults is even more difficult. A power supply
current monitor for detection of enhanced power supply current in ECL devices
is presented.
An IDDQ-Fault Location Scheme
Tsin-Yuan Chang, Weihong Chen, National Tsing Hua University, Hsinchu,
Taiwan, ROC
In this work, an IDDQ-fault location scheme is proposed to locate single
faulty power branch (a VDD branch, or a GND branch, or both) or a faulty
region surrounded by a VDD branch and a GND branch by using hardware approach,
which can be applied to the redundant VLSI structure for yield enhance ment
in the repairable design.
World Wide Web-Based Automatic Testing of Analog Circuits
Clinton D. Knight, Stephen P. DeWeerth, Georgia Institute of Technology,
Atlanta, Georgia, USA
We present a World Wide Web-based interface that enables characterization
of microelectronic devices and circuits from a remote location. The testing
system promotes efficient sharing of auto mated test equipment among a large
body of users. It is already being used at Georgia Tech for both engineering
education and analog circuit research.
Automatic Test Generation Software to Detect Single Contact Faults in
a Programmable Logic Array
Edwin Jimenez, Luis Maldonado, Rubi V. Valentin, Alfredo Cruz, Polytechnic
University of Puerto Rico, Hato Rey, Puerto Rico
The purpose of this report is to present an automatic test generation software
to detect single contact faults in a PLA. The software is a simplified implementation
of the algorithm Pradip Bose presented in this thesis (3) using C++.
A New Approach in the Implementation of Test Generation Algorithms for
Programmable Logic Arrays
Mahamudh Shideh, Jacqueline Ortega, Raymond Sanchez, Alfredo Cruz, Polytechnic
University, Hato Rey, Puerto Rico
A new approach was used in the development of the implementation of a minimal
test vector genera tion algorithm (1) for single and multiple fault detection
in a PLA. The conversion of product terms from binary notation to decimal
notation simplifies the developments of the C language subroutines used
for the implementation.
MA2.3 Neural Networks I - N. Al-Holou, Hoda S. Abdel-Aty-Zohdy, Chairpersons
- Scheman Room 260
Network Based on SOM (Self-Organizing-Map) Modules combined with
Statistical Decision Tools
Daniel Graupe, Hubert Kordylewski, University of Illinois, Chicago, Illinois,
USA
The neural network described in this paper is concerned with storage and
retrieval of large memories. It employs features such as forgetting, interpolation,
extrapolation and filetering. The network's operation is analyzed through
a case study of an application to a simulated medical diagnosis problem.
A Neural Network Approach to Circuit Extraction
Q.J. Zhang, F. Wang, Carleton University, Ottawa, Ontario, Canada
A new application problem, i.e., circuit extraction, for neural networks
is developed in this paper. A new formulation to represent the circuit extraction
problem by numerical pattern recognition is proposed. Multilayer perceptrons
(MLP) are utilized to learn the circuit information and to use this knowledge
to extract the circuit macromodels.
Uncertain Nonlinear Algebraic Solutions and their Implementations using
Neural Networks
Hoda S. Abdel-Aty-Zohdy, M.A. Zohdy, M. Karam, Oakland University, Rochester,
Michigan, USA
In this article, we propose a dynamic recurrent approach to solve uncertain
nonlinear algebraic equations. The approach is justified on the basis of
net construction that recursively produces minimum neuron state energy which
corresponds to the desired solution. Linearization via Newton -Raphson method
is employed in order to make the net converge to appropriate region in the
solution space. Some preliminary experimentation on non-trivial nonlinear
examples are included and discussed. Approaches for hardware implementation
of the recurrent dynamic neural network will be presented. Comparison between
a totally digital chip design and a hybrid analog/digital implementa tion
utilizing MOSIS facilities is made. Evaluatiion and simulations on system,
logic, and circuit levels are emphasized.
Analysis of Process Variation Effects on a CMOS Bidirectional Associative
Memory
Ashfaq Aslam, Bob Mack, University of Essex, Colchester, Essex, United
Kingdom
This paper discusses the results of an analysis of the effects of process
variation for a CMOS bidirec tional associative memory (BAM); the most significant
factors being transistor parameter variation in threshold voltage, mobility
and oxide thickness. Monte-Carlo simulation has been carried out for a range
of process deviations and for different sizes of BAM; this has enabled bounds
to be estab lished on the process parameter deviation allowable, for a specified
size of BAM, for correct recall in the presence of a specified bit-error
in the input data.
MA2.5 Video Coding and Compression - Ajai Narayan, Chairperson
- Scheman Room 275
Variable-Size Pruned Discrete Cosine Transform Routine for Video
Compression
Mohamed El-Sharkawy, Michael Polakowski, Purdue University, Indianapolis,
Indiana, USA
Digital video signals require large amounts of data to represent them. Much
of the data is redundant, both spatially and temporally. Many ideas for
eliminating that redundancy and hence conveying a given amount of information
with less data have been proposed. Recently, the Moving Pictures Experts
Group (MPEG) has released a standard for video compression which relies
heavily on the computation-intensive methods of block-based transforms and
motion estimation. We review the standard, including the discrete cosine
transform (DCT) and motion compensation (MC) sections.
An alternative transform, the pruned DCT (PDCT), is introduced and compared
to the DCT in terms of computational expense and resulting image quality.
Advantages and disadvantages of the PDCT in terms of computational savings
and image quality, are presented.
Subband Image Compression using Wavelet Transform and Vector Quantization
Mohamed A. El-Sharkawy, Christian A. White, Purdue University, Indianapolis,
Indiana, USA
The Discrete Wavelet Transform (DWT) has many useful properties when applied
to image compres sion. The multiresolutional decomposition is of complexity
O(n) and conserves the geometric image structure within each subband. A
tree-structured coding scheme can efficiently exploit the inherent correlation
in the subband representation. An algorithm is introduced which incorporates
a fast tree -structured quantization scheme and partial search vector quantization.
The algorithm described in this paper is a novel quantization thresholding
scheme which uses the DWT to decompose an image into octave wide frequency
bands, then quantizes the coefficients using a "look ahead" measurement
of the image based on the low frequency sub-image inherent in the DWT. This
algorithm then uses vector quantization to code the thresholded coefficients
of the decomposed image. A partial search vector quantization algorithm
is used to increase the speed of the quantization by using a sorted table
of the energy content of the code vector. Each subband has an associated
codebook which is gener ated using the Pairwise Nearest Neighbor (PNN) algorithm
to produce an initial codebook and then uses the Generalized Lloyd (GL)
algorithm to arrive at a final codebook.
An Efficient Lossless Image Compression Scheme for Hierarchical, Block-by-Block
Trans mission
M. Das, Oakland University, Rochester, Michigan, USA; J. Nethercott,
F.W. Rahrig, Rome Laboratory, Griffiss Air Force Base, Rome, New York, USA
A hierarchical, block-by-block image coding scheme based on a suboptimal
adaptive multiplicative autoregressive model is introduced in this paper.
The appealing features of the proposed method includes: i) ease of implementation,
ii) higher compression than an existing technique called hierarchi cal interpolation,
and iii) capability of selective reconstruction of desired areas of interest
in a scene.
Spatial/Temporal Interpolation for Very-Low-Bit-Rate Video Transmission
Kin Keung Fung, Bing Zeng, The Hong Kong University of Science and Technology,
Hong Kong
In this paper, we develop several interpolation methods that have taken
into consideration both spatial and temporal correlations. We apply these
interpolators in very-low-bit-rate (less than 64 kb/s) video transmission
based on a decimation/interpolation scheme we proposed earlier. We found
that, we this scheme and newly developed interpolators, it is quite feasible
to transmit video sequences with CIF format at VLBR where H.261 is used
as the baseline codec.
A Model Based Motion Estimation Algorithm for Very Low Bit Rate Video
Coding
Her-Hsiung Chang, Long-Wen Chang, Chen Duei Huang, National Tsing Hua
University, Hsinchu, Taiwan, ROC
A new algorithm for very low bit-rate image sequences coding with low bit-rate
and high picture quality is proposed. The proposed algorithm uses a variable
block size method to estimate motion vectors accurately and reduce the number
of motion vectors. Unlike conventional algorithms, the proposed one applies
a multi-vectors algorithm to estimate a block motion by more than one motion
vector and uses a model based method to trace the object's contours to reduce
visual artifacts. By testing several image sequences, such as "Miss
American" and "Claire", the proposed algorithm shows very
good results.
MA2.6 Communications Networks and Fault Tolerance - M. Alam, Chairperson
- Scheman Room 250
The Use of Adaptive Fault Tolerance in General Classes of Linear
Systems
J. Jiang, C. Schmitz, B.A. Schnaufer, W.K. Jenkins, University of Illinois,
Urbana, Illinois, USA
Several recent publications have developed the concept of adaptive fault
tolerance (AFT) by demon strating how adaptive filter architectures and
adaptive algorithms can be designed to continue operating effectively in
the presence of such failures. Previous studies limited the use of AFT to
one -dimensional FIR filter structures. This paper further develops the
concept of AFT for one-dimensional IIR filter structures, and also for two-dimensional
FIR structures, demonstrating that indeed AFT can be extended to these more
general classes of linear systems.
High-Order Covariance Analysis for the Classification of Facsimile Signalling
Tones on the General Switched Telephone Network
S.R. Alty, A.R. Greenwood, Liverpool John Moores University, Liverpool,
United Kingdom
A method is presented for detecting and classifiying facsimile signalling
tones on the general switched telephone network. It was found that by using
high-order covariance analysis it is possible to detect the onset of 'V.27ter'
and 'V.29' data rapidly at signal-to-noise ratios lower than 15dB.
Property Verification and Performance Evaluation of Communication Protocols
Based on Probabilistic Reachability Analysis
Mario Baldi, Enrico Macii, Massimo Poncino, Politecnico di Torino, Torino,
Italy
In this paper we show how symbolic probabilistic analysis techniques for
finite state systems can be successfully used to perform quantitative verification
of properties and performance evaluation of communication protocol layers
and, more in general, of entire protocol stacks and complete commu nication
networks. In particular, we first outline our approach to the problem of
verifying communica tion protocols, and we then present an application example
of the proposed methodology to the simple Alternating Bit Protocol.
A Heuristic Strategy for Dynamically Controlling the Time Slot Access
in Reservation Communication Protocols
Alberto Macii , Enrico Macii, Politecnico di Torino, Torino, Italy
In this paper we present a new technique for determining the time slot assignment
in a reservation protocol which out-performs existing approximate approaches
concerning accuracy and computation time.
The Packet Loss Analysis in The Manhattan Street Network
Antonio Augusto T.P. de Moraes, Luan Ling Lee, DECOM/FEE/UNICAMP, SP,
Brasil
In this article, we conducted a theoretical analysis of the packet loss
in the Manhattan Street Network (MSN). The concepts of network capacity
and capacity rate introduced. In order to prevent nodes from losing untransmitted
packets, we also proposed the use of queues in the MSN. In addition, we
introduced a statistical model to the MSN with buffering. Based on our model,
we derived expres sions for some performance statistics which explicitly
show the performance of the MSN. To validate our approach, we compared the
results from solving the model to those obtained from simulations. The results
of the packet loss analysis suggests that the MSN operates below the capacity
rate to achieve the best performance.
MA2.7 Computer Networks - Douglas Jacobson, Chairperson - Scheman
Room 208
All-Optical Dense WDM Wide-Area Communication Network
Shiu C. Chan, Minghua Lu, Satish S. Udpa, Lalita Udpa, Doug W. Jacobson,
Iowa State University, Ames, Iowa, USA
This paper describes a high capacity, scalable and modular all-optical dense
WDM WAN. The network assumes a ring-tree (tree of rings) topology and employs
all-optical packet switching, wavelength reuse, conversion, and routing
schemes for data transport. The optical fiber four-wave mixing (FWM) nonlinear
phenomenon is used for wavelength conversion, and erbium-doped fiber amplifiers
(EDFAs) are used for signal amplification, in the network. The proposed
network can be implemented at various scales, from a LAN to a global communication
framework. Its transport protocols can be adapted for any dense wavelength-reuse
WDM network.
Efficient Multicasting and Broadcasting in Wormhole Networks
Phanindra K. Mannava, South Dakota School of Mines and Technology, Rapid
City, South Dakota, USA
Efficient broadcasting and multicasting are two of the most important primitives
in shared memory multiprocessors. We propose an efficient hardware algorithm
for multicasting and broadcasting in wormhole routed hypercube networks
and show how to extend it to a mesh. The efficiency is shown by implementing
the algorithm for cache coherence in shared memory multiprocessors.
ATM Switching Systems for Broadband ISDN
Sukant K. Mohapatra, Frank D. LaRocca, AT&T Bell Laboratories,
Lincroft, New Jersey, USA
An ATM switching system consists of various modules in addition to the switch
fabric which is primarily used to route the cell inside the switch. In this
paper, an integrated view of the ATM switching system is proved with various
modules classified as per the functionality of different planes of B -ISDN
protocol reference model they support. The design and implementation issue
of these various modules and their interworking is the primary focus of
the paper.
Issues in Networked Multimedia Services
Shervin Erfani, M. Malek, Lucent Technologies, Middletown, New Jersey,
USA
Future multimedia network services will provide integrated voice, graphics,
text and video seamlessly on integrated transport networks. A key facet
of this new paradigm is the need for application interoperability and quality
of services. These issues have been investigated and a generic architec
ture of multimedia network services is proposed. Key communication environment
requirements aimed for multimedia services, including storage capacity,
transport requirements, and performance tradeoffs are investigated. Access
strategies to networked multimedia services, including ISDN and cable modem
access are discussed.
Call Admission Control for Variable Bit Rate services in ATM Networks
H. Baraka, Cairo University, Cairo, Egypt; H. Mohsen, M.El Sherif, Electronics
Research Institute, Cairo, Egypt
This paper integrates the problem of call admission together with Bandwidth
and Buffer allocation. The proposed Call admission technique is based on
finite buffer model and heterogeneous services with gaussian distribution
and different service durations. Two bandwidth allocation techniques are
proposed for the call admission control. The performance evaluation of the
proposed technique via simulation shows the effectiveness of the proposed
method.
MA2.8 Linear and Nonlinear Stability - Dale Brandt, Chairperson -
Scheman Room 204
Conditions for Stability of Cascaded Two-Ports Networks with Feedback
Dale R. Brandt, Rockwell International, Cedar Rapids, Iowa, USA; Robert
J. Weber, Iowa State University, Ames, Iowa, USA
Cascaded amplifiers pose a difficult problem with respect to stability calculations,
especially in MMIC design. The common power supply can be a source of feedback
between stages, rendering the initial stability calculations for each stage
inaccurate. A new method to analytically determine the exact amount of allowable
feedback before a circuit becomes potentially unstable is presented.
Eigenvalues and the Linville Power Plane Stability
Harry C. Gundrum, Maher E. Rizkalla, Purdue University at Indianapolis,
Indianapolis, Indiana, USA
An analysis of the properties of an ellipse using linear algebra to define
eigenvalues of general 2D systems is applied to determine the stability
of a particular system, the Linvill power plane. This is an old but useful
geometric approach to analyzing power flow, power gain, and stability in
amplifer design.
Thermodynamic Approach of Energy Conversion in Parametric Transformers
Cesare Mario Arturi, Politecnico di Milano, Milano, Italy
The aim of the paper is to present a thermodynamic approach of the theory
of the energy conversion in inductive parametric converters. An inductive
parametric converter, also named parametric transformer (PT), is a static
electromagnetic device made by two nonlinear inductors having zero mutual
inductance. The coupling of the constitutive equations, needed by the conversion
process, is due to the nonlinearity of the magnetic medium.
Applying Energy Equations for Analysis of Cycloconverter Operation
I. Katz, M.A. Slonim, Ben-Gurion University of the Negev, Beer-Sheva,
Israel
Analysis of cycloconverter and simulation are difficult because it is a
nonlinear structure. Large number of intervals and different control angles
are occured during one period of cycloconverter operation. A new method
for the analysis and computer simulation of cycloconverters is proposed.
The method is general for various forms of cycloconverter, the analysis
is not depended on type or topology of cycloconverter. Lagrange equations
are used to obtain differential equations governing cycloconverter processes.
The developed method allows us to obtain the instantaneous currents and
voltage for different cycloconverter topologies.
Amplitude Stabilization in a Triangular Wave Quadrature Oscillator
Eva Vidal, Alberto Poveda, Eduard Alarcon, Universitat Politecnica De
Catalunya, Barcelona, Spain The application of phase plane concepts
for designing quadrature oscillators is a well-known technique in the field
of sine, square or triangle wave generators. The simple circuits that had
been reported as triangular generators [1]-[2] are based on conservative
equations that don't describe the starting transient and the amplitude stabilization.
In this paper the slew-rate of the operational amplifier and the limited
output voltage of the integrator that performs the circuit implementation,
are showed to be the responsible for the starting and the stabilization
of the waveform generators.
MA2.9 Signal Classification - Satish Udpa, Chairperson - Scheman
Room 299
Two-Stage Neural Network for Blind Sources Separation
Sueng-Jin Choi, Ruey-Wen Liu, University of Notre Dame, Notre Dame, Indiana,
USA
The separation of the independent sources from an array of sensors without
the knowledge of channel characteristics is a fundamental problem encountered
in many applications. This paper provides a two-stage neural network which
adaptively recovers the source signals from sensor outputs. The learing
algorithms for the network proposed, consist of the self-normalizing decorrelation
and the extended Oja's rule. This network performs the simultaneous diagonalization
of the 2nd-order and 4th-order moment matrices of sensor outputs for the
reconstruction of the source signals.
Multilayer Neural Network Classification of On-Line Signatures
N. Mohankrishnan, Wan Suck Lee, Mark J. Paulik, University of Detroit
Mercy, Detroit, Michigan, USA
The incorporation of neural network classification strategies to enhance
the performance of an autoregressive (AR) model-based signature classification
system is examined. A multilayer perceptron trained using the back-propagation
algorithm is used for classification. Results obtained using an extensive
database of signatures are presented.
A Discrete Wavelet Model for Target Recognition
Yung-Da Wang, Mark J. Paulik, University of Detroit Mercy, Detroit, Michigan,
USA
In this work a parametric multiresolution technique which utilizes a wavelet
basis expansion of object planar contours over a discrete time-scale space
is used for target identification. Preliminary classifi cation results indicate
that the approach described provides robust identification of target contours
under a broad range of aspects.
A Classifier System with Low Sensitivity to Pattern Shifted Position
Luis Nino-de-Rivera, Mariko Nakano-Miyatake, Juan C. Sanchez-Garcia,
Hector Perez-Meana, Universidad Autonoma Metropolitana, Iztapalapa, Mexico;
Edgar Sanchez-Sinencio, Texas A&M University, College Station, Texas,
USA
Recently an increased activity has been reported in machine recognition
of faces, numerous advances have been made in the design of statical and
neural network classifiers. Classical ideas such as Karhunen-Loeve transform
based method have been reported. However, hardware dedicated systems such
as VLSI neural network classifiers are expected to provide better performance,
although most of them still presents several problems when the input patterns
position is different to that of the reference ones. This paper presents
an alternative for proposal for dedicated hardware classifier with low sensitivity
to changes in the position between the input and reference patterns. The
implementa tion of proposed structure seems to be feasible for VLSI integrated
circuit.
Fast Particle Discriminator Based on Matched Filters
J.M. Seixas, L.P. Caloba, L.A.F Pinto, COPPE/EE/UFRJ - CP, Rio de Janeiro,
Brazil
A fast discriminator for high-energy particles is developed using matched
filters. It is based on analysing the time structure of electron and pion
signals from a scintillating fiber calorimeter, a detector that measures
the energy of the particles. The discriminator is able to achieve discrimina
tion responses within 100 ns and for a beam energy of 80 GeV, less than
0.05\% of pions are misclassified as electrons for an electron efficiency
of more than 99\%. This represents an improve ment of more than 50\% in
the discrimination efficiency obtained by using a standard constant fraction
discriminator.
12:00 - 1:30 pm Symposium Luncheon - Scheman Room 220 - 240
How to Wake Up Your Creative Genius!
William C. Boon, Professor of Landscape Architecture , Iowa State
University, Ames, Iowa (see special guest speakers, page 67)
1:30 - 3:30 CONCURRENT SESSIONS
MP1.1 Analog Circuits and Driver Design - R. Johnston, Chairperson
- Scheman Room 167
A Compact High Frequency VLSI Differential Analog Adder
Alejandro Diaz-Sanchez, Centro Nacional de Investigacion y Desarrollo
Tecnologico Interior Internado Palmira S/N, Cuernavaca, Morelos, Mexico;
Jaime Ramirez-Angulo, New Mexico State University, Las Cruces, New Mexico,
USA
Design and implementation of a VLSI voltage adder for low voltage applications
is described. The compactness of the proposed approach allows the addition
of two high frequency voltage signals for applications in both: continuous
time and sample data filters. Such operations are made with a good low-distortion
performance. The voltage adder is designed for 2 µ m nwell technology.
Effects of SSN on CMOS Output Driver Design
Srinivasa R. Vemuru, The City College of The City University of New York,
New York, New York, USA
CMOS output buffers are used to drive large off-chip capacitances. Higher
frequency of operation, simultaneous switching of the output drivers and
the parasitic inductance present at the pin-pad -package interface results
in significant switching noise (SSN). The effect of SSN on overall buffer
propagation delay, taper factor and transition time is discussed.
Single 5V Silicon BJT and CMOS Laser Drivers for a Multipoint to Point
Passive Optical Network at 155.52 Mbit/s
R. Coppoolse, University of Gent-IMEC, Gent, Belgium
Both a silicon BJT and CMOS laser-driver IC for a multipoint to point passive
optical network at 155.52 Mbit/s are presented. Both circuits are optimised
for low power dissipation and low cost. When fully assembled with commercially
available packaged laserdiodes, optical rise-and fall-times smaller than
1.2 ns are demonstrated over a 0-50 mA output current tuning range.
A Highly Linear Cascode Driver CMOS Source-Follower Buffer
Kh. Hadidi, A. Khoei, Urmia University, Urima, Iran
Traditionally CMOS technology lacks a simple open-loop buffer like emitter-follower
of bipolar technology. The simple source-follower buffer suffers from channel-length
modulation of the driver device as the main source of harmonic distortion.
In this article we present a novel source-follower buffer that its driver
device is cascoded. Thus, the circuit can improve harmonic distortion up
to 20dB relative to conventional one.
A High Speed Analog 50W Line Driver in Digital CMOS Technology
Robert F. Payne, J. Alvin Connelly, Georgia Institute of Technology,
Atlanta, Georgia, USA
A single-ended analog buffer designed to drive 50 ohm loads is described.
The circuit consists of a common source output pair driven by a pair of
differential error amplifiers which significantly reduce the output impedance.
This technique improves the drive capability of conventioanl CMOS operational
amplifiers. This paper demonstrates the feasability of the circuit as a
stand alone buffer.
MP1.2 CAD for Digital Circuits - Liang-Fang Chao, Chairperson - Scheman
Room 262
An Improved Analytic method to Calculate Emitter Follower Delay
Including Emitter Resistance
E.J. Brauer, University of Kentucky, Lexington, Kentucky, USA
As bipolar transistor size decreases, emitter resistance becomes increasingly
important in estimating transient delay. We use a quasi-linear large-signal
bipolar junction transistor model and linear trial functions in coupled
node equations to calculate delay of emitter followers including the effect
of emitter resistance. When compared to SPICE simulations, our method produces
accurate low-to-high delays for a factor of 10 increase in emitter resistance.
An Improved Object-Oriented Framework for Simulation
Albert Davis, Lucent Technologies, Allentown, Pennsylvania, USA
This paper presents an improved object-oriented architecture for circuit
simulation in C++, as imple mented in the simulator "ACS".
Conservative Modeling of the Contribution of Spurious Transitions to
Power Dissipation in Digital CMOS VLSI Circuits
Christophe Tretz, Charles Zukowski, Columbia University, New York, New
York, USA
A number of CMOS design choices, such as the choice of logic family, require
a general model of the fraction of logic transitions that arise from glitching.
Analysis and simulation of a ripple-carry adder is used to derive a conservative
model for static circuits. Across most applications, a good conservative
estimate is 30-40%.
Modeling Timing Correlation and the Accurate Timing Verification of Digital
Interface Circuits
Marco A. Escalante, University of Victoria, Victoria, British Columbia,
Canada
Recent research on timing verification of digital interface circuits has
implicitly assumed that the delays of different signal transitions in the
circuit are independent of one another. However timing diagrams in data
sheets clearly specify timing correlation. If correlation is ignored, the
results of verification can be overly pessimistic. In this paper we propose
a probabilistic timed Petri net capable of representing timing correlation.
For the sub-class of periodic nets with AND and OR causality we develop
a procedure that not only checks accurately if each one of the given timing
constraints is satisfied but also determines the probability that a particular
timing constraint would be violated.
A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation
Tianwen Tang, Xing Zhou, Nanyang Technological University, Singapore
A dynamic delay model, which includes the nonlinear loading effect, the
effects of the input transition time and the multiple-input triggering,
is proposed for the gate-level timing simulation. It is shown that the developed
delay model gives near circuit-level accuracy with comparable speed to other
common delay models.
MP1.3 Neural Networks II - Hoda S. Abdel-Aty-Zohdy, Chairperson -
Scheman Room 260
Nonlinear Control of Solar Power System
James A. Momoh, Yanchun Wang, Howard University, Washington DC, USA
In this paper, we apply the direct linearization method to design the ac/dc
converter controller of solar power system. The simulation results show
that the system oscillation caused by the step increase in load and the
fault can be efficiently damped by the designed controller. The designed
controller is of the idea robustness.
Power System Preventive Control Using Artificial Neural Networks Based
Generation Rescheduling Method
James A. Momoh, Chris B. Effiong, Howard University, Washington DC, USA
In this paper, a fast method for computing generation rescheduling for preventive
control using artificial neural network (ANN) and transient energy margin
(EM) is presented. A two stage multilayer feed forward ANN is used first
to obtain the system energy margin and the sensitivities with respect to
the initial generation and second to obtain the generation reschedule. The
method is tested on 39-bus system and the result compared with security
constrained OPF.
Identification of Contaminating Particles in Air Using Artificial Neural
Networks
Paula A. de Souza Jr., Universidade de Brasilia, Brazilia, D.F., Brazil;
O.D. Rodrigues, Universidade Federal do Espirito Santo, Vitoria, E.S., Brazil;
T. Morimoto, Companhia Siderurgica de Tubarao, Serrra, E.S., Brazil; V.K.
Garg, Laboratory of Material Science, Brasilia, D.F., Brazil; K. Nomura,
University of Tokyo, Tokyo, Japan
The present investigation consists of an application of Artificial Neural
Networks (ANN) that were trained with data from several analytical techniques
for the identification of particulate matter in atmospheric aerosols in
the Metropolitan Region of Vitria -MRV- (1461 Km2 , with nearly one million
habitants and houses more than 400 industries.) ES, Brazil.
Multivariable System Decoupling Through Neural Networks Precompensation
Jose Maria Galvez, Marcos de Oliveira Fonseca, Federal University of
Minas Gerais, Brazil
A major difficulty in multivariable control design is the cross- coupling
between inputs and outputs which obscures the effects of a specific controller
on the overall behavior of the system. This paper considers the application
of neural networks in decoupling multivariable output feedback controllers.
Simulation results are presented to show the feasibility of the proposed
technique. A general proce dure for control design is suggested.
Multivariate Statistical Modeling of ATM Traffic Flows for Adaptive Control
with Neural Networks
Alexandru Murgu, University of Jyvaskyla, Jyvaskyla, Finland
In broadband ATM networks, the traffic generated by a wide range of sources
having diverse charac teristics is subject to different performance constraints
when passing through the communication system. This is so because the statistical
multiplexing of the bursty traffic flows generates buffering delays and
losses during the transportation through the network. To improve the utilization
of network resources and provide a higher degree of flexibility in handling
different classes of traffic, an adaptive control approach for smoothing
the traffic assignments among the competing classes of users is considered.
In this paper, a multiple class discrete-time queueing model is developed
for describing the mutual correlation between different traffic patterns,
when the buffer size is finite. The cell arrivals from users are assumed
to be aggregated during the statistical multiplexing and to satisfy a general
distribution of the batch size and a geometric distribution for the interarrival
times between batches. The traffic control mechanism enforces a smooth distribution
of waiting times and is implemented as a neural network controller. This
traffic controller allows a dynamic operation of the adaptive schedules
(receding horizons) within a sampling interval and has a useful pattern
tracking feature. The neural network controller consists of a two level
mapping: the control mapping (for receding horizon schedules) and a tracking
mapping (for detecting the flow pattern changes). Some numerical results
show the performance of the traffic controller for bursty ATM flows.
MP1.5 Signal Processing Algorithms and Applications I - Solomon Ghorayeb,
Chairperson - Scheman Room 275
Source Localization by 2-D Root-MUSIC with Scalar Triads of Velocity-Hydrophones
Kainam T. Wong, Michael D. Zoltowski, Purdue University, West Lafayette,
Indiana, USA
This paper introduces a new and computationally efficient direction finding
(DF) algorithm that (1) exploits the velocity vector-field information of
impinging wave front (vs. only pressure scalar wavefield), (2) estimates
both elevation angles and azimuth angles, (3) requires rooting only two
polynomials and no costly iterative searches. This paper successfully adopts
the Root-MUSIC algo rithm to L-shaped arrays of triads of co-located but
orthogonally oriented velocity hydrophones. Each velocity hydrophone measures
one Cartesian component of the acoustic velocity vector -wavefield. In one
two-signal scenario, this new algorithm increases estimation accuracy by
about 3 folds and lowers the resolution threshold by 25dB SNR relative to
comparable pressure-sensor arrays that fail to recognize the vector-field
character of the acoustic wave-front.
A New Number System for Faster Multiplication
Reza Hashemian, Northern Illinois University, DeKalb, Illinois, USA
A new ternary number system, called Bit-Signed Number (BSN), is introduced.
Some properties and application of BSN is discussed. It is shown that, in
fact, the well known Canonic Sign Digit (CSD) number is a special case of
a BSN number, and it is obtained by minimizing the number of non-zero digits
in a BSN number. Conversion of a 2's complement number to its equivalent
BSN and also to CSD number system is developed, and the application of CSD
number in high speed multiplication is discussed.
Using Transputers to Implement Signal Recovery Algorithm Based on Higher
Order Statis tics
Jun Liu, Boon-Hee Soong, Nanyang Technological University, Singapore
The higher order cumulants and their Fourier transforms, polyspectra are
used in order to achieve a number of objects which may not be possible to
obtain using second order statistics. In this paper, we study different
approaches to estimate the bispectrum and apply the result to the reconstruction
of signal with noise. The major obstacle of using higher order statistics
in signal processing is the requirement of large amount od data and computational
power. We discuss the result of using various transputer networks to accelerate
the processing speed.
Details on the Equivalence of the Modified FBLP Method and TLS-FBLP method
Rodrigo Pinto Lemos, Amauri Lopes, State University of Campinas, FEEC-DECOM,
Campinas-SP, Brazil
This work analytically shows that the total least squares (TLS) solution
to FBLP method is equivalent to a minimum norm solution with SVD truncation
in both the data matrix and the observation vector. However, the Modified
FBLP solution is not equivalent to the TLS solution.
MP1.6 Logic Circuits - Peter Aronhime, Chairperson - Scheman Room
250
Techniques for Reduced Power and Increased speed in dynamic- and
ratio-logic circuits
Paul Kartschoke, Norman Rohrer, IBM Microelectronics Division, Essex
Junction, Vermont, USA Three approaches are used to increase the usefulness
of dynamic-and ratio-logic circuits by eliminat ing DC power or increasing
speed. The first significantly reduces the power of predischarged ratio
-logic circuits by sensing the voltage of the ratioed node and eliminating
the DC current, which realized an 86% reduction in DC power. The second
improves the speed of a dynamic- and ratio-logic circuit by partitioning
the heavily loaded common node. Here, speed improvement of 26% to 42% is
shown. Finally, an approach is disclosed that implements a low-threshold
voltage NFET to improve the speed of a dynamic circuit.
Comparison of a Wide Range of Differential CMOS Logic Topologies
Christophe Tretz, Sudhakar Ranganathan, Charles Zukowski, Columbia University,
New York, New York, USA
Most existing differential CMOS logic circuits, including ones based on
pass logic, are carefully classified by topology, and some new variations
are obtained. The breakdown of design into distinct decisions allows more
meaningful performance comparisons. A study based on local comparison of
energy-delay product is provided as an example, and various extensions are
discussed.
Subthreshold Current-Mode Differential Logic Circuits for Low Power Digital
Systems
Mark N. Martin, Philippe O. Pouliquen, Andreas G. Andreas, Martin E.
Fraeman, The John Hopkins University, Baltimore, Maryland, USA
A Current-Mode Differential Logic scheme is introduced. By biasing in the
subthreshold regime, the transistors are operated with maximum normalized
transconductance, gm/I. The rapid saturation of devices operated in subthreshold
allows for radical scaling of supply voltages to only a 300mV. Application
of a back-bias further increases the gm/I of the transistors, and hence
the gain of the gates. The back bias also assists in the reduction of stray
junction and gate-bulk capacitance. Operating with small voltage swings,
delays of a few hundred nanoseconds can be achieved with bias currents of
50nA. This results in operational speeds of a few megahertz at greatly reduced
power consumption compared to standard CMOS digital logic. Experimental
results are presented and extrapolated to a scaled version of the circuit.
Digital Design of Higher Radix Quaternary Carry Free Parallel Adder
A.T.M. Shafiqul Khalid, A.A.S. Awwal, O.N. Garcia, Wright State University,
Dayton, Ohio, USA
A high speed parallel full adder is designed which can perform carry-propagation-free
addition of two modified signed digit quaternary numbers. The adder has
been designed based on a mathematical model developed in the present work.
On Implementation of Fast, Bit-Serial Loops
Mark Vesterbacka, Kent Palmkvist, Lars Wanhammar, Linkoping University,
Linkoping, Sweden
In this paper we show that it is not sufficient to specify the latency of
the processing elements to arrive at a maximally fast implementation of
a recursive algorithm. We demonstrate how higher throughput is obtained
for a first-order recursive filter by increasing the latency of the processing
elements.
MP1.8 RF Microwave Devices and Circuits - Douglas Anderson, Chairperson
- Scheman Room 204
Bipolar Active Inductor Realizability Limits, Distortion, and
Bias Conditions
Douglas P. Anderson, Electronic Technology Corporation, Ames, Iowa, USA;
Robert J. Weber, Steve F. Russell, Iowa State University, Ames, Iowa, USA
Active inductors for MMICs offer an interesting alternative to passive implementations
when the rf currents are below the threshold levels needed to maintain low
distortion. This paper examines the limits of realizability for a MMIC inductor
circuit that utilizes two bipolar junction transistors in a common collector-common
emitter configuration to gyrate the base-emitter capacitance of the common
emitter stage to form a synthetic inductor. The inductance range, Q-factor,
distortion, dc bias points, and dc power consumption for the circuit are
considered. Governing equations and graphs describing circuit performance
are presented. The results show that the goals of higher Q, lower distortion,
and good DC power utilization are not conflicting in terms of the biasing
of the transistors.
Non-linear Properties of PHEMT Transistors Exploited in the design of
active RF/Microwave Frequency Multipliers
Donald G. Thomas Jr, G.R. Branner, University of California, Davis, California,
USA
A prerequisite for the realization of active frequency multipliers is the
existence of a nonlinear device having sufficient efficieny for generation
of the desired frequency multiple. This may be realized by any device in
the classes of BJT, FET, etc. In the literature, there exists very little
on the development of frequency multipliers exploiting the nonlinearities
of the PHEMT transistor. This paper discusses and presents for the first
time, in a quantitative manner, the nonlinearities of the PHEMT device which
makes it a desirable candidate for frequency multiplier design. Conversion
gains of 6 dB have been obtained for specific multiplier realizations.
Novel Operating Condition of Class E Frequency Multiplier Which Enables
50% Duty Ratio
Tadashi Suetsugu, Fukuoka University, Fukuoka, Japan
The analysis and design equations of the class E frequency multipliers with
the switching duty of 50% are presented in the case of their outputs are
even harmonics, i.e., multiples of 2, of the switching frequencies. The
circuits can be operated by the same driving method as the class E amplifiers.
Experimental results from 1.05MHz 2.2W frequency doubler are shown to verify
the results of the theoretical analysis.
Subnanosecond High Current Switching With Low-Ohmic Load by Application
of Drift Step- Recovery Diodes
S. Vainshtein, A.F. Ioffe Institute, St. Petersburg, Russia; J. Kostamovaara,
K. Maatta, A. Kilpela, University of Olulu, Finland
Fast recovery of the voltage across the semiconductor diodes has allowed
to obtain 100 A current pulses across the low-ohmic load with the rise time
in subnanosecond range. Further dI/dt increase is predicted, provided the
diode structure is further optimized.
An Improved Planar Balun Design for Wireless Microwave and RF Applications
B. Preetham Kumar, G.R. Branner, G. Razmafrouz, University of California,
Davis, California, USA
This paper describes an improved microstrip coupled line balun design for
use primarily in the exploding wireless market. The two main advantages
of this design are its compact size, which is a fraction of the standard
l/4 coupled line design, and extremely tight coupling of ~ 4 dB at 900 Mhz,
over an appreciable bandwidth.
MP1.9 Linear Circuits I - William Black, Chairperson - Scheman
Room 299
Designing Spice-Predictable, Single-Stage, Bipolar-Junction-Transistor
Amplifiers Richard R. Johnston, Lawrence Technological University,
Southfield, Michigan, USA
The proposed method for designing amplifiers whose performance matches the
design criteria (as measured by Spice simulation), uses a reduced version
of the Gummel-Poon static model of the transistor in the forward active
region to model the vBE vs. iC relation and the iC vs. iB relation.
Design of High-Accuracy CMOS Oversampling Current Sample/Hold (S/H) Circuits
Renyuan Huang, Christoph Gruenewald, Chin-Long Wey, Michigan State University,
East Lansing, Michigan, USA
This paper presents the design consideration of a CMOS oversampling current
sample/hold (S/H) circuits. The circuit adopts an integrating feedback structure
which reduces the error of the current copier, where the copier is used
to sample the input current. The S/H circuit is comprised of an integrator
and a current copier. The performance of S/H circuit depends on the current
copiers it used. This paper addresses some design issues on developing high-accuracy
S/H circuits.
BiCMOS Cascaded Bandgap Voltage Reference
I.M. Filanovsky, Sean S. Cai, University of Alberta, Edmonton, Alberta,
Canada
A bandgap voltage reference with a circuit providing compensation of the
thermal nonlinearity for the base-emitter voltage is described. The temperature
dependence of Vbe(T) is linearized using for the bias current a sum of two
currents one of which is proportional to the third degree, and another to
the forth degree of temperature. The simulation shows that the approach
allows to obtain the reference voltage with the temperature coefficient
of 7 ppm/degC in the -40 to +170 degC temperature range.
An Integrated Low-Noise BiCMOS Amplifier Channel and Timing Detector
Tarmo Ruotsalainen, Pasi Palojarvi, Juha Kostamovaara, Tero Peltola,
University of Oulu, Oulu, Finland
An integrated low-noise differential BiCMOS transimpedance amplifier channel
with gain contro, peak detector, rms-noice meter and timing detector has
been designed for a portable laser rangefinding device. The measured BW=10
Mhz, Z=2.7 MW and input referred noise 0.9 pA/ . The walk error of the timing
detector is +/-50 ps (7.5 mm) when its signal amplitude changes from 150
mV to 2.5 V.
Virtual Dynamic of DC Circuits
Dalibor Biolek, Zdenek Biolek, Military Academy Brno, Czech Republic
This contribution deals with the stability testing of DC operating points
of networks with controlled sources, especially with the operational amplifiers.
The possibility of utilization of the principle of virtual shifting in the
network analysis is pointed out. It is shown that the special space of virtual
dynamics of DC circuit exists in which the stability of DC operating points
can be investigated using so-called virtual eigenvalues and virtual trajectories.
MP1.10 Applications, Optical Systems and Robust Control - Erwei Bai
and Jeff Echtenkamp, Chairpersons - Scheman Room 171 - 179
Robust Realizations and Transformations
Surjit S. Mahil, Purdue University Calumet, Hammond, Indiana, USA
In the analysis and design of control systems, various algorithms employ
well-conditioned similarity transformations, such as unitary and Householder
transformations. The solution is then the exact solution of a nearby model.
In this paper, an alternative well-conditioned and robust similarity transformation
- to transform a matrix (in companion form) to a parity-normal matrix, is
developed. The transformed matrix is robust with parity-normal eigenvectors.
The developed similarity transfor mation is not available in the literature.
It is anticipated that the transformation will prove very helpful in the
design of well-conditioned algorithms for the modern analysis and design
of control systems.
A Robust Adative Control System for Poorly Known Large Dimension Plants
José Maria Gálvez, Federal University of Minas Gerais,
Belo Horizonte, M.G., Brazil
This paper presents a model reference adaptive controller for poorly known
large dimension systems. The control algorithm is based on the concept of
pole dominance in the frequency domain. Condi tions for asymptotic stability
are established through Lyapunov's theory without constraining the plant
to be strictly positive real (SPR). It is shown that the proposed scheme
is asymptotic stable inside of a relatively large neighborhood of the nominal
plant dynamics. Simulation results illustrate the regulation and tracking
outstanding performances of the proposed scheme.
On the Synthesis of Robust Controllers VIA Thirty-Two Edge Theorem
C.J. Munaro, DEL - CT - UFES, Vitoria, E.S., Brazil; P.J. Oliveira, UNEB
- CETEBA - DCE, Vitoria E.S., Brazil
The problem of robust stabilization of uncertain systems defined by interval
plants is analyzad. Based on classic control compensation technics, properties
deduced from the thirty-two edge theorem and geometry of value set of closed
loop polynomials of an interval plant, a methodology for the synthesis of
stabilizing controllers is proposed.
Optical Fiber Video Transmission using Pulse Time Modulated Subcarrier
and Optical Coherence Modulation of Light
A. Torres-Fortiz, C. Gutierrez Martinez, H. Ramirez-Leyva, Instituto
Nacional de Astrofisica, Mexico
Pulse Time Modulation (PTM) subcarriers have been extensively studied for
optical transmission of analog video signals. PTM subcarrier normally modulates
optical intensisty of light which is transmit ted via an optical fiber channel.
An alternative to optical intensity modulation is coherence modula tion
of light thus promoting multiplexed transmission of several PTM subcarriers
over only one optical fiber. PWM and coherence modulation of ligth will
be presented at the symposium.
Burst-Mode 16 QAM Receiver for Upstream Transmission over CATV Networks
X. Wang, X.Z. Qiu, Peter Lambrecht, J. Vandewege, K. De Meyer, W. Trog,
University of Gent, Gent, Belgium
This paper describes the characteristics and performance of a burst-mode
16 QAM receiver. Circuit implementations and control algorithms are presented
with an emphasis on burst-mode phase acquisition, automatic gain control,
and data decision. Measurement results show a typical receiving sensitivity
of -60dBm, a dynamic range of 22dB and a run-in time of 2us.
Efficient Microcontroller Based Portable Heart Monitoring System
Mohammad S. Alam, Amitava Chatterjea, Patrick Ferriter, Purdue University,
Fort Wayne, Indiana, USA
An inexpensive, portable, and easy to use heart monitoring system was designed
and developed. This device could be worn by a person while exercising or
at any other time. When in operation, it monitors the appropriate part of
the EKG signals from the heart continuously. This instrument also has the
capability to alert the user whenever an abnormal heart rhythm occurs storing
the signal simultaneously for the future diagnosis of the problem by a specialist.
Template Matching for Local Guidance System
Jamal Rahhal, Yu-Lin Wang, Guillermo E. Atkin, Illinois Institue of Technology,
Chicago, Illinois, USA
In this paper we describe an important component of an Interactive Assistance
System designed to help the blind and visually impaired to become more independent,
increasing their mobility and ability to work. A major part of the system
is a Local Guidance System (LGS) that uses image processing techniques to
extract the most important features in the path of the blind. The LGS provides
informa tion to the user about obstacles and general characteristics of
the walking path. It uses two miniature cameras to capture the image from
two different locations. A processor uses a template matching algorithm
to detect the main features in the path. Then the images are processed and
delivered in an (text to speech) audio format. The objects are chosen and
classified by a statistical study of an actual street images, then the templates
are formed for each main feature in the image by averaging all the images
obtained for that feature.
A New VLSI Hardware Algorithm For Centroid Computation
D. Ma, E. Johnson, J. Ramirez-Angulo, New Mexico State University, Las
Cruces, New Mexico, USA; A. de Luca, CINVESTAV-IPN, Mexico
A new hardware algorithm for centroid detection has been developed. This
algorithm is simple and fast, and is easy to implement with software or
hardware. A VLSI hardware implementation is discussed. SPICE simulation
shows that the circuit can determine the centroid of an object within less
than 100 ns for a 32-bit input.
System Modeling Using A Second-Order Volterra Delay Filter
Li-Zhe Tan, Iterated Systems, Atlanta, Georgia; Jean Jiang, Interactive
College of Technology, Atlanta, Georgia, USA
In this paper, we extend the linear delay filter to a second-order Volterra
delay filter to include the linear and quadratic filter coefficients for
system modeling and identification. According to the error surface analysis,
we propose two algorithms. The techniques are specially effective in modeling
second-order Volterra systems with sparse system coefficients.
Hypergraphs in VLSI Planariztion
Valeri Feinberg, Electrical Engineering University, Minsk, Belarus; Artour
Levin, Intel Corporation, Santa Clara, California, USA
This paper is devoted to the hypergraphic models of circuits, to the mathematical
methods of their planarization and to the practical questions of the CAD
system construction on their base. The present work concentrates on "essentially"
hypergraph models of circuits and their planarization techniques as the
most adequate.
An Efficient Line Algorithm
A.T.M. Shafiqul Khalid, Ascent Solutions Inc., Fairborn, Ohio, USA; M.
Kaykobad, Bangladesh University of Engineering & Technology, Dhaka,
Bangladesh
We present a new algorithm for drawing lines in a raster device in which
a suitable data structure has been chosen to avoid comparisons that are
required, for example, in Bresenham's algorithm. Experi mental results as
well as clock cycles calculated theoretically suggest that this new algorithm
outper forms the ones currently existing in the literature in terms of computational
time. Our experimental results also suggest that quality of the line does
not deteriorate even when high resolution raster devices are used.
3:30 - 4:00 pm Refreshment Break - Scheman First Floor Lobby
4:00 - 6:00 CONCURRENT SESSIONS
MP2.1 Digital Hardware - J. Ramirez-Angulo, Chairperson - Scheman
Room 167
A New Fast Multiplier Architecture
Emad Abu-Shama, Mohamad Maaz, Magdy Bayoumi, The University of Southwestern
Louisiana, Lafayette, Louisiana , USA
In this paper a new multiplier architecture is proposed for low power and
high speed applications. It is based on generating all partial products
in one step, then summing these partial products using binary tree network.
This reveals a speedup of more than 50% than the array multiplier for (32X32)
bit multiplication. Computer simulation with HSPICE shows that the new proposed
architecture has better speed and power performance.
A Novel High-Speed Parallel Muliply-Accumulate Arithmetic Achitecture
Employing Modified Radix-4 Signed-Binary Recoding
Vishwas M. Rao, Behrouz Nowrouzian, The University of Calgary, Calgary,
Alberta, Canada
This paper is concerned with the design and implementation of a novel high-speed
signed-binary (SB) parallel multiply-accumulate arithmetic architecture.
The resulting architecture employs a new modified-radix-4 SB recoding technique
for the reduction of the number of intermediate partial products in conjunction
with carry-free nested additions for the high-speed generation of the full
-precision multiply-accumulate product. A novel rounding technique is proposed
for the concurrent rounding of the multiply-accumulate product (in accordance
with IEEE Standard 754) and the corre sponding overflow correction. The
resulting multiply-accumulate arithmetic architecture is verified by Viewlogic
simulations using the parameters of the Actel 1.2 micron technology.
A Novel Approach to the Design and Implementation of a Very High-Speed
Digit-Serial Modified-Booth Multipliers
Vishwas M. Rao, Behrouz Nowrouzian, The University of Calgary, Calgary,
Alberta, Canada
A novel approach is presented for the design and implementation of digit-serial
modified-Booth multipliers. In this approach, the partial product sum components
are represented in their signed -binary (SB) format while the corresponding
intermediate partial product components are represented in their two's complement
(TC) format, permitting very high-speed carry/borrow free multiplication.
A novel technique is presented for IEEE Standard 754 rounding of the full-precision
SB product. The proposed modified-Booth multipliers permit very high thoughputs
for arbitrary values of digit size, are highly area-time efficient for large
digit sizes, and lead to uniform implementations with highly localized interconnections
making them suitable for VLSI. These multipliers have been verified using
Viewlogic simmulations for the Actel 1.2µ FPGA technology.
VLSI Implementation of a Fast Radix-4 SRT Division
Chin-Long Wey, Cheng-Ping Wang, Michigan State University, East Lansing,
Michigan, USA
This paper presents a fast radix-4 SRT division architecture. Instead of
finding the correct quotient digit, a quotient digit is first estimated.
The estimated quotient digit is used to simultaneously compute the two possible
partial remainders for the next step while the quotient digit is being corrected.
Since the decision making circuits can be implemented with simple gate structures,
the proposed divider offers fast speed operation. Based on the physical
layout, the circuit takes 265 ns for a double precision division (56 bits
for fraction part), where the 2mm SCMOS technology in MAGIC is employed
and simulated.
Fast Externally Asynchronous - Internally Clocked Systems: - Internally
Clocked Systems:
Implementation and Analysis of a New Genre of Self-Timed Circuits
Jacob L. Bell, Richard F. Tinder, Mark Manwaring, Washington State University,
Pullman, Washington, USA
Defying the timing defects and limitations imposed on traditional asynchronous
circuits, the externally asynchronous - internally clocked (EAIC) system
provides the digital designer a new tool for construct ing self-timed circuits.
Based on a revolutionary memory unit, the architecture lends itself nicely
to sequential design, where a typical EAIC system may require less power,
use less hardware, and operate at much greater speeds than comperable synchronous
designs. This paper describes the analysis of several circuits and culminates
in the comparison of simulation and actual test results.
A Controller Chip for a Scaleable ATM Switch Node
Paul Shipley, Michael Weeks, Magdy Bayoumi, University of Southwestern
Louisiana, Lafayette, Louisiana, USA
This paper presents a control chip for a 16 x 16 switching node for the
distributing banyan network. This chip enables the use of a larger and much
more efficient switching node than was previously available. Very high performance
is required of the chip and thus a number of special circuits have been
created to achieve this performance. The chip has been designed in 1.0 micron
CMOS using a mixture of static and dynamic logic.
MP2.4 Analysis Methods - Laurence Huelsman, Chairperson - Scheman
Room 252
A Novel Tool for Circuit-System Modeling
Robert W. Sandage, J. Alvin Connelly, Georgia Institute of Technology,
Atlanta, Georgia, USA
A novel method of modeling and simulating circuits and systems has been
developed using LabVIEW software. Complex analog circuits are modeled by
their behavioral equivalent. Mixed-mode systems, which are typically problematic
for conventional simulators such as SPICE, are easily simulated without
excessive overhead. Examples of a voltage comparator macromodel and sigma-delta
modulator system are described.
Analysis of Noise Parameter Extraction from Noise Figure Measurements
J. Sanderson, G.R. Branner, B. P. Kumar University of California, Davis,
California, USA
The accuracy of noise parameter estimation of an active device is limited
by uncertainties in the noise figure measurements and errors in the source
admittance data. In this paper, a qualitative and graphical assessment is
made of the sensitivities and estimation errors of the noise parameters
over the two-dimensional source admittance grid.
Steady-State Small-Signal Analysis of Switched Capacitor Circuits
Hannu Jokinen, Martti Valtonen, Helsinki Univesity of Technology, Otakaari,
Finland
This paper presents a steady-state small-signal analysis method for nonlinear
circuits. The method can be used to calculate the steady-state time domain
representation as well as the frequency response of switched capacitor circuits.
Any nonideal models for switches can be used, i.e., all modeling levels
of MOSFETs as switches including parasitic components can be simulated.
The method proposed may be applied to mixer analysis for the case of a strong
LO and a weak RF signal to calculate a steady-state solution, a spectrum,
or a conversion gain. An example is given to demon strate that the method
proposed is efficient and sufficiently fast to simulate switched capacitor
circuits. The simulation results show good agreement with transient analysis.
A Novel Waveform Analyzer for Analog and Digital Signals for the Windows
Environment
P.R.B. Pinto, C. E. T. Oliveira, M.L. Anido, Universidade Federal do
Rio de Janeiro, Rio de Janeiro, Brazil
This paper presents a novel waveform analyzer tool for signals specified
in the analog or digital form, for the Windows environment. Differently
from ordinary analyzers, that just present the contents of a file in graphics
form, without providing more sophisticated functions, this system incorporates
powerful signal analysis functions, allowing, for example logic operations
among signals, trigger condition specification and signal superposition.
This tool can operate as a waveform analyzer server for several client simulators,
using advanced protocols for process communication (DDE) for the Windows
environment.
Multiple Output terminal Reliability for Circuits
H. Singh, H.S. Sekhon, Wayne State University, Detroit, Michigan, USA;
Lisa Anneberg, Lawrenece Technological University, Southfield, Michigan,
USA; E. Yaprak, Wayne State University, Detroit, Michigan, USA; D. Kaur,
University of Toledo, Toledo, Ohio, USA
It is proposed to utilize a new approach for determining multiple output
terminal reliability of commu nication circuits. The approach represents
the multiple output terminal paths of given circuits in the form of minterms;
and then a switching theoretic approach is used so as to result in non-overlapping
simplification of multiple output Boolean functions. The technique will
give disjoint terms in which the branch reliability value can be substituted
and the multiple output reliabilities are determined.
MP2.5 Signal Processing Algorithms and Applications II - To be announced,
Chairperson - Scheman Room 275
Sparse Array Aperture Extension with Dual-Size Spatial Invariances
for ESPRIT-Based Direc tion Finding
Kainam T. Wong, Michael D. Zoltowski, Purdue University, West Lafayette,
Indiana, USA
A novel sparse array geometry embedding two sizes of spatial invariances
is proposed for use with a new ESPRIT-based algorithm for aperture extension.
This novel direction finding method extends array aperture without additional
antennas, without irregular inter-element spacings, and without any cyclic
ambiguity in the final arrival angle estimates. The half-wavelength invariance
yields unambigu ous but high-variance DOA estimates to disambiguate low-variance
but cyclically ambiguous esti mates from the larger invariance. Under a
particular simulation scenario with two closely spaced uncorrelated narrowband
sources, the proposed algorithm offers an astounding two {\em orders of
magnitude} improvement in estimation standard deviation and bias and $50$dB
reduction in resolu tion threshold, relative to a customary half-wavelength
array of comparable hardware and software complexity. Any additional computation
needed by this method may be performed in parallel, thereby requiring no
serious increase in overall computational time.
EEG Signal Compression With ADPCM Subband Coding
Zlatko Sijercic, Gyan C. Agarwal, Charles W. Anderson, Colorado State
University, Fort Colllins, Colorado, USA
An EEG signal compression method that combines both octave-band filter bank
frequency decompo sition and coding in subbands using ADPCM is proposed.
Besides being computationally effective, this compression method in its
simplest form yields 70% data reductions with very little distortion. Higher
compression rate are obtained by increasing the order of the predictor used.
A "Signal Processing Based Model" for Time Reponse Reduction
in Industrial Sensors
Gholam H. Riahy, MONASH University, Clayton, Melbourne, Australia
Dealing with the time constants of the sensors in fast going processes including
slow actuators, in this paper, we have proposed a new method to reduce the
delays involve with the sensors. The proposed method not only reduces the
time responses of the temperature, pressure and humidity sensors, but also
keeps the precision within the accepted level. The key feature is a modified
case of linear prediction which is based on the modelling of the sensors.
In this modelling we have a first order system, a dead band delay and presence
of random noise.
Artefact's Filtering from Human EEG
Michaela Kofronová, Biolek Dalibor, Brno Military Academy, Czech
Republic
The computer EEG data processing is modern trend in medical data processing.
This paper is dedicated to solving of removing artefacts of physiological
origin in EEG data and gives complex solution of artefact filtering from
adaptive segmentation of EEG signal over type of artefact identification
of each segment of signal to adaptive filtering.
Rule Learning in Fuzzy Systems Using Evolutionary Programs
J. Goddard, UAM-I, Iztapalapa, Mexico; R. Urbieta Parrazales, CINTEC-IPN,
Mexico; I. Lopez Cruz, UACH, Mexico; A. de Luca P., CINVESTAV, Mexico
The present paper considers the problem of learning a set of optimised rules
and membership functions for the case of a rule-based fuzzy controller of
a simulated d.c. motor. The method we apply uses two evolutionary programs.
The first program produces a minimal set of rules according to a suitable
fitness function. The second then adjusts the membership functions to obtain
a reduced error. We present comparisons of the method for different sized
rule-bases, and contrast the results with a PID controller for the d.c.
motor.
MP2.6 Data Converters I - Randall Geiger, Chairperson - Scheman
Room 250
A 3.3V-70MHz Low Power 8 bit CMOS Digital-to-Analog Converter with
Two-Stage Current Cell Matrix Structure
Ji Hyun Kim, Kwang Sub Yoon, Inha University, Incheon, Korea
This paper describes a 3.3V-70MHz low power 8 bit CMOS digital to analog
converter (DAC) designed with a 4 MSB current matrix stage and a 4 LSB current
matrix stage. The two stage current cell matrix architecture allows the
designed DAC to reduce not only a complexity of decoding logic, but also
a number of current sources.
An 8-bit 42MSamples/s Current-Mode Folding and Interpolation CMOS Analog-to-Digital
Coverter with Three-Level Folding Amplifiers
Kyung Myun Kim, Kwang Sub Yoon, Inha University, Incheon, Korea
An 8-bit current-mode folding and interpolation A/D Converter with three-level
folding amplifiers is presented. A three-level folding amplifier is designed
not only to reduce the number of reference current sources, but also to
decrease a power dissipation within the A/D Converter. The simulation results
illustrate a conversion rate of 42MSamples/s and a power dissipation of
30mW.
A 6-mW 10 Bit, 300 kSamples/s Pipeline A/D-Converter
Antti Mantyniemi, Timo Rahkonen, Antti Ruha, University of Oulu, Oulu,
Finland
A 10 bit, 300 kS/s pipeline A/D converter, having a 5 clock cycle conversion
time and consuming 2mA from a single 3 V supply is designed. The circuit
was fabricated in a 0.8 um CMOS process, and measured effective number of
bits (ENOB) using a digital RSD type error correction was typically 9.3.
The size of a 1-bit cell is 220 um x 440 um.
A GaAs-HBT A/D Gray-code Convertor
S. Megherbi, Universite de Paris-sud, France; C. Dubon, P. Launay, France
Telecom/CNET, France; J.F. Pone, Universite de Paris-sud, France
A monolithic bipolar GaAs-HBT Analog-to-Digital converter is presented.
The architecture approach is based upon a parallel conversion method. It
relies on a structure mixing conventional flash con verter elements without
using a complex output logic transcoder. We reached more 1G-samples/s sampling
rate, with a resolution of 3-bits. The future step will be to lead to improvement
the compro mise frequency/resolution of this structure in our GaAs-HBT process
development.
A High-Speed A/D Converter Architecture for High-Resolution Applications
Nadder Hamdy, Arab Academy for Science & Technology, Alexandria,
Egypt
A high resolution A/D converter architecture is presented. It combines the
excellent speed perfor mance of the flash quantization technique with the
hardware simplicity of cyclic and cascaded con verter architectures. The
effectiveness of the technique is illustrated through a 14-bit example where
the output word is generated in two cascaded modules with minimum speed
loss due to cascading.
MP2.7 Fuzzy Systems - Julie Dickerson, Chairperson - Scheman Room
208
Minimum-Order Fuzzy Relation of a Closed-Loop System
Cezary Kolodziej, Roland Priemer, The University of Illinois at Chicago,
Chicago, Illinois, USA
Using the fuzzy relational matrix model of a process and the fuzzy relational
matrix of a controller, a new method for obtaining the fuzzy relational
matrix of a closed-loop system with an external input is given. The presented
method has the advantage that it produces a closed-loop system minimum -order
fuzzy relation matrix. The included example shows that the method is easy
to implement.
Self-Learning Neurofuzzy Controller
Chunshien Li, Roland Priemer, University of Illinois at Chicago, Chicago,
Illinois, USA
A fuzzy logic inference procedure, that is stuctured in the form of a feedforward
neural network, is employed to control a plant in a unity feedback closed-loop
system. Certain neural network nodes are introduced to accommodate control
of multiple-input-multiple-output plants. The network
learning algorithm is a modified random search procedure, which does not
require a model of the plant. Weights of the network are adjusted in accordance
with linguistic rules about the input/output behavior of the plant being
controlled.
Fuzzy Saturating Control of a Ball and Beam System
J. Glower, J. Munighan, North Dakota State University, Fargo, North Dakota,
USA
In this paper, a connection between fuzzy controllers and variable structures
controllers is developed. With this connection, a proof of their stability
is presented. Further, methods to simplify fuzzy controllers as well as
apply them to situations where fuzzy controllers previously failed are developed.
A Fuzzy Block Replacement Algorithm for Disk Caches
Ravi Pendse, Udo Walterscheidt, Seng Choy Kua, Wichita State University,
Wichita, Kansas, USA A new block replacement algorithm for disk caches
is presented. The Fuzzy Block Replacement Algorithm (FBRA) uses fuzzy rules
to pick out the block to be evicted when an I/O reference causes a miss
on a filled up disk cache. Trace driven analysis, based on commercial data,
was used for simulation and the results were compared to existing algorithms.
Fuzzy Modelling of an Experimental Flexible Arm
A. Cuce', G. Grasso, G. Sortino, C. Vinci, Fuzzy Logic R & D and
Application Group, Co. Ri. M. Me., SGS-Thomson, Catania, Italy
In this paper a fuzzy model of an experimental flexible arm is presented.
The identification of the fuzzy model parameters is performed on a combined
associative+neuro-fuzzy network. Position and vibration measures have been
taken on the real system to create the training patterns for the network,
implementing the fuzzy model of the non linear system. The data acquisition
has been performed by using a very low sensor equipment. A description of
the combined network and the learning algo rithms is provided. The identification
results are shown and the response of the fuzzy model and of the real system
to the same stimulus are compared.
MP2.8 Innovative Approaches to Teaching Power - Shelli Starrett,
Chairperson - Scheman Room 204
Applying Cooperative Learning to a Graduate Power System Analysis
Course: It Works For Me!
Richard D. Christie, University of Washington, Seattle, Washington, USA
This paper gives anecdotal experience about the application of cooperative
and active learning concepts in a graduate class in power system analysis.
The use of these techniques resulted in a significant improvement in student
evaluations of the course (and the instructor!) in comparison with two prior
offerings.
Introducing Power Systems in an Undergraduate Machines Lab
Thomas W. Gedra, Oklahoma State University, Stillwater, Oklahoma, USA
To illustrate the complexity of power system operation to juniors in Energy
Conversion I, a simple power system was constructed using fractional-horsepower
machines. Students then operated the system both with and without connection
to the grid. The lab setup and student activities are described. Other improvements
to the OSU undergraduate power curriculum are also discussed.
Development and Application of a Power System Simulation Environment
T.J. Overbye, R.P. Klump, J. Weber, University of Illinois U-C, Urbana,
Illinois, USA
This paper describes a user-friendly power simulation package for teaching
power system operations and control. This Microsoft Windows based program
simulates power system operation over a specified time period (of typically
several hours to a day). Students dynamically interact with the simulated
system through various windows, including a one-line display. The use of
the data files and option windows allows the program to simulate a wide
variety of different power systems and operating problems.
Power System Engineering at the Sophomore Level
J.D. McCalley, V. Ajjarapu, G.B. Sheble', V. Vittal, Iowa State University,
Ames, Iowa, USA
This paper presents a course in power system analysis developed for offering
at the sophomore level as a part of the required undergraduate electrical
engineering curriculum at Iowa State University. We describe the criteria
used in developing the course, the topical coverage, and a set of computer
modules, developed to facilitate learning of particularly difficult concepts
while heightening student interest, that run in the MATLAB environment.
A Virtual Electromechanical Machine Simulator
K. Olejniczak, T.W. Martin, W.G. Johnson, University of Arkansas, Fayetteville,
Arkansas, USA
This paper presents an interactive virtual electromechanical machine simulator
designed to be an effective pedagogical tool for the undergraduate and graduate
program. It has a user-friendly graphical interface and consists of two
distinct controller and electric machine modules. A virtual permanent-magnet
brushless machine controlled by a six-step inverter is presented in detail.
A Multi-Institutional Cooperative Approach to Power Engineering Education
M.L. Crow, S.D. Sudhoff, University of Missouri Rolla; Rolla, Missouri,
USA; A. Pahwa, S. Starrett, Kansas State University, Manhattan, Kansas,
USA; K. Olejniczak, University of Arkansas, Fayetteville, Arkansas, USA
This paper will describe a multi-institutional project which has been undertaken
by the three partici pating universities to develop two senior-level courses
in flexible power system control.
MP2.9 Linear Circuits II - Igor Filanovsky, Chairperson - Scheman
Room 299
Simple Rail-to-Rail Constant-Transconductance Input Stage Operating
in Strong Inversion
Vladimir I. Prodanov, Michael M. Green, State University of New York
at Stony Brook, Stony Brook, New York, USA
A CMOS op-amp input stage operating in strong inversion with common-mode
range beyond rail- to-rail is described. It uses two complementary differential
pairs connected in parallel. The common -mode dependent current biasing
employs only four transistors, does not require additional voltage references,
current switches and/or current mirrors and does not increase the minimum
required supply voltage. The variation of the net transconductance is approximately
15% over the entire common-mode range. Simmulation and experimental results
are included.
A New CMOS Differential Amplifier Circuit for Improved Slew Rate Performance
Mark E. Pulkin, J. Alvin Connelly, Georgia Institute of Technology, Atlanta,
Georgia, USA
A new differential amplifier topology has been developed which improves
slew rate performance without requiring large, quiescent bias currents.
This new differential amplifier input stage has been incorporated in a CMOS
operational amplifier which achieves slew rates above 50 volts/microsecond
with bias power dissipation in the low microwatt range.
A 3-V Power Supply, Decades-Tunable Range OTA and Its Applications in
Signal Process ing
Shang-Ching Dong, Michael M. Green, State Universtiy of New York at Stony
Brook, Stony Brook, New York, USA
Using a simple voltage subtractor combined with cross coupled differential
pairs, a low power supply, wide tunable range, high linearity transconductor
is designed. Channel modulation effect of transistors is examined and cancelled
by a cross biased transistor pair. Common mode feed-back scheme is presented.
Due to the high linear tunability, the new designed trans -conductor also
works as current mode multiplier. Simulation results show that the power
supply voltage can be as low as 3V or less. The linear tunable range is
more than 2 decades, dynamic range is about 70dB and cut-off frequency is
10mhz. The design trade-off between linear input and tunable range are described.
The maximum differential input voltage that device can handle is 1.6V. Thanks
to high programmability, the transconductor presented here can be imple
mented for various applications. Finally, a second order lowpass filter
is built whose passband can tuned from 10KHz to 1.6MHz.
A 3 - V High Supply Rejection Bandgap Voltage Reference with Novel Trimming
Sandhya Gupta, William Black, Iowa State University, Ames, Iowa, USA
A 2 micron CMOS bandgap voltage reference capable of operating with a 3
Volt power supply is described. This circuit uses a novel n-well trimming
scheme and internal shunt regulation in order to achieve a high supply rejection
precision reference in about .15 sq. mm.
A Package for Circuit Analysis in Symbolic Form with Mathematica
Ali M. Eydgahi, University of Tehran, Tehran, Iran
In this paper we present a package in MATHEMATICA environment. All circuit
responses are available in Laplace domain and in symbolic form. The circuit
response to various signals defined by user or obtained from output of any
system can be determined symbolically and also graphically. Sensitivity
analysis can be done on the specified expressions for variation of any parameters.
MP2.10 Applications, Multiprocessors and Computational Algorithms - Akhilesh
Tyagi and Soha Hassoun, Chairpersons - Scheman Room 171 - 179
Granularity Experiments for the Adaptive MultiProcessor System (AMPS)
D.L. Tao, Bradley S. Carlson, N.W. Lo, Zhu Zheng, State University of
New York at Stony Brook, Stony Brook, New York, USA
AMPS (Adaptive MultiProcessor System) is a shared-memory MIMD architecture
intended for digital signal processing applications. We present our investigations
on task granularity for AMPS. We have investigated task decomposition (granularity
reduction) for matrix multiplication and fast fourier transform (FFT) and
task grouping (granularity enlargement) for Gram-Schmidt orthogonalization
(GSO). The results indicate that significant performance improvement can
be obtained for matrix multiplication and GSO by selecting the appropriate
task granularity.
Fault Tolerant Algorithms for Broadcasting on the Star Graph Network
Bradley S. Carlson, D.L. Tao, N.W. Lo, State University of New York at
Stony Brook, Stony Brook, New York, USA
Fault tolerant algorithms are presented for broadcasting on the star graph.
In our algorithm fault tolerance is achieved by constructing an isomorphism
of the network such that the faulty nodes minimally disrupt the message
passing sequence. It is shown that in the presence of r(1 =< r =<
k-2) faults at most r extra steps are required by our algorithm to perform
a one-to-all broadcasting in the k-star network. Our algorithm has the same
time complexity as an optimal broadcasting algorithm, and since it takes
advantage of the hierarchical nature of the star graph network, it can be
imple mented easily. Our algorithm can also be used to perform all-to-all
broadcasting in a faulty star graph.
Performance-driven Interconnection Allocation
A. Mezhoud, J-C. Dufourd, N. Darbel, Ecole Nationale Superieure des Telecommunications,
Paris, France
This paper addresses the problem of performance-driven interconnection synthesis
in a bus based VLSI architecture. We present the inter-dependence problem
between interconnection allocation and floorplanning, and we give a new
approach to interconnection synthesis based on a two step tech nique. The
first step consists in communication-oriented floorplanning, which places
components in architectural level while minimising the communications cost.
The second step consists in assigning communications to interconnections.
It minimises the propagation delay by balancing the loads on the interconnections
and reducing their estimated lengths.
A New Multi-Dimensional Network Architecture Arranged in Alternated Regular
Mesh Fashion
Lee Luan Ling, State University of Campinas (UNICAMP) - Brazil; Alberto
J. Centeno Filho, Federal University of Goias (UFG), Brasil
This paper presents a new multi-dimensional network architecture arranged
in alternated regular mesh fashion with toroidal boundaries. Performance
and cost parameters are analyzed for the best adaptation of the network
dimension. The possibility of making use of the proposed network in computer/processors
interconnection a and broadband switching architectures applications is
investigated.
A Distributed Cache Memory for Multiprocessors Based on the Crossbar
Interconnection Principle
Michael Lindig Bos, Ed. de Graduados de la UPIICSA, Granjas, Mexico
A distributed cache memory scheme for shared-memory multiprocessors based
on a modified crossbar interconnection network is described. It is shown
that N inquiry quests may be serviced simultaneously, where N is the number
of processors. The operation protocol of the cache memory is discussed,
and performance evaluations are presented. For cache hits, the architecture
approaches the ideal model of the PRAM (parallel random access machine),
in the sense that all processors have simultaneous access to shared memory.
An Algorithm for Multiplication Modulo (2^N-1)
Zhongde Wang, G.A. Jullien, W.C. Miller, University of Windsor, Windsor,
Ontario, Canada
This paper proposes an efficient algorithm for multiplication modulo (2^N-1).
To achieve high speed, the Wallace tree is adopted for the multiplier. The
Wallace tree multiplier exhibits a more regular structure than binary Wallace
tree multipliers, and comparisons with published designs demonstrates advantages
of our multiplier architecture in both speed and hardware.
An Efficient 3-Modulus Residue to Binary Converter
Zhongde Wang, G.A. Jullien, W.C. Miller, University of Windsor, Windsor,
Ontario, Canada
An efficient algorithm which converts the residue number, with moduli set
{2^N-1, 2^N, 2^N+1}, into an equivalent binary number, is introduced. The
algorithm improves on a preciously published technique. A novel hardware
implementation is also discussed. In comparison to the cited converter,
the hardware savings are in excess of 66% ad a reduction of 30% in the critical
path is obtained.
A Parallel Architecture for Arithmetic Coding and Its VLSI Implementation
Horng-Yeong Lee, Leu-Shing Lan, Ming-Hwa Sheu, Chien-Hsing Wu, National
Yunlin Institute of Technology, Taiwan
A new parallel architecture for arithmetic coding is presented in this paper.
By dividing the input symbols into a number of groups and processing them
in parallel, significant speedup can be achieved in comparison with existing
architrctures. The advantages of this parallel architecture are its easier
expandability, higher speed, and smaller latency. The parallel arithmetic
coder has also been implemented on VLSI using the VHDL technique. The resultant
chip layout has a size of 4993x6503 squared sum.
An FFT Processor Based on the SIC Architecture with Asynchronous PE
J. Melander, T. Widhe, Kent Palmkvist, Mark Vesterbacka, L. Wanhammar,
Linkoping University, Linkoping, Sweden
A SIC architecture with asynchronous bit-serial PEs is presented and applied
to the ST-FFT algorithm. The resulting architecture can easily be modified
for higher throughput and/or lower power consump tion. Using this architecture
a high-performance chip for use in an OFDM transmission system has been
designed.
Characterization of Parallel Architectures for Object-Oriented Languages
Michael Orlovsky, Kamal Jabbour, Syracuse University, Syracuse, New York,
USA
We present results of the characterization of parallel architectures for
the execution of algorithms developed using object-oriented languages. Object-oriented
analysis and design is applied to soft ware to yield reusable, reliable,
and portable code. Care must be taken to structure the software for efficient
execution while avoiding implementation dependencies that bind the software
to a specific parallel architecture. Characterization results for several
relevant parallel machine architectures will be described based on algorithms
coded in C++.
On the Impact of Encoding Rotations on Area and Power Dissipation of
Finite State Machines
Massimo Poncino, Politecnico di Torino, Torino, Italy
The problem of state assignment for finite state machines has been extensively
studied by the synthesis community, targeting traditional criteria like
area, performance, testability, or, more recently, power dissipation. State
assignment algorithms targeting low power dissipation try to assign states
so as to minimize the Hamming distance between state code, thus reducing
the switching at the latch inputs. The resulting encoding is not unique,
and there are many other encodings called rotations, which are equivalent
from the power dissipation standpoint. Proper selection of the representative
encoding may significantly affect the area, and, in its turn, the dissipated
power itself. In this paper we show the quantitative impact of these rotations
on the final design in terms of area and power, and a criterion for selecting
"good" rotations, avoiding their explicit enumeration.
Low-Power State Assignment for Asynchronous Finite State Machines
Ming-Der Shieh, Wann-Shyang Ju, Ming-Hwa Sheu, National Yunlin Institute
of Technology, Yunlin, Taiwan, ROC
In this paper a precise model for calculating the state transition probabilities
of asynchronous finite state machines (AFSMs) is presented. Based on this
model, an efficient race-free state assignment technique is introduced to
minimize the average switching activities of state variables, thus, to reduce
the power dissipated during state transitions in AFSMs.
A Mixed Two Level Execution Model for Parallel Nested Loops
H.M. Moharram, Cairo University, Cairo, Egypt; S.M. Nassar, Electronic
Research Institute, Giza, Egypt
Since parallel loops in parallel programs provide the greatest potential
of parallelism to be exploited by multiprocessor systems, it is reasonable
and effective to focus our attention on parallel loops. This paper concentrates
only on the problem of dynamic processor assignment for arbitrary nested
parallel loops. A two-level processor self-scheduling scheme for general
nested loops is presented. Also, an algorithm is provided to be used by
the compiler to distribute the loop iterations on a number of processes,
such that the parallel execution time of the entire loop construct is minimized.
Cost Effective Parallel Processor Assignment Approach (CEPA)
Aida O. Abd El-Gwad, Salwa M. Nassar, Rasha E. Tawhid, Electronic Research
Institute, Giza, Egypt
In recent years, parallel computing has been enhanced by the availability
of many commercial multiprocessors. However, many questions are still unanswered
such as how many processors to use, or what is the best partitioning and
scheduling. Not only increasing the number of processors in a multiprocessor
system increases the speedups obtained by executing parallel programs on
these processors, but also there are several other important issues that
affect the speedups. One of those issues is determining how to schedule
independent processors to execute a parallel program as fast as possible.
KH-map: A New Way of Representing the Hypercube Structure
A.T.M. Shafiqul Khalid, Wright State University, Dayton, Ohio USA; Mohammad
S. Alam, Purdue University, Fort Wayne, Indiana, USA; A.A.S. Awwal, Wright
State University, Dayton, Ohio, USA
Binary hypercube is an attractive and powerful topology for interconnecting
computing nodes in a multiprocessor system since it allows simple deadlock-free
routing and broadcasting. In a hypercube architecture one has to visualize
multidimensional objects to develop an efficient algorithms or to analyze
system behavior, whereas, human beings are habituated to at most three-dimensional
objects. In this paper, we propose a novel two-dimensional representation
of the hypercube structure. The proposed representation is used to design
routing and broadcasting algorithms. Finally, a comparison of the proposed
representation with the conventional representation is elucidated.
Adaptive IIR Filtering Using Modified Homotopy Continuation Method
Sangmin Bae, Lalita Udpa, Satish Udpa, Iowa State University, Ames, Iowa,
USA
Infinite-length impulse response (IIR) filtering based on least mean square
output error approach has met with the problems of convergence to local
minima. The purpose of this study is to develop an algorithmic approach
for solving problems associated with convergence to the local minima in
adaptive IIR filtering using a numerical method called homotopy continuation
method. First, the homotopy continuation method are modified in order to
solve a set of nonlinear polynomials with time-varying coefficients. Then,
adaptive IIR filtering is formulated with a set of nonlinear polynomi als
starting from mean square output error minimization approach. An iterative
filtering algorithm is derived from the modified version of the homotopy
continuation method, utilizing the polynomials expression. Simulation results
for a system identification example show the proposed algorithm find filter
coefficients at a global minimum position.
GEEP: A Low Power Genetic Algorithm Layout System
Glenn Holt, Akhilesh Tyagi, Iowa State University, Ames, Iowa, USA
In this paper we present GEEP, a genetic algorithm for low power standard-cell
placement. GEEP reduces interconnect capacitance by an average of 20\% over
recursive min-cut area optimizing placement. It incorporates a number of
heuristics to produce good placements fast relative to existing GAs, including
a novel method for handling low population diversity. We tested GEEP on
a suite of MCNC benchmarks and found this hybrid approach successful in
producing good post-placement results in a reasonable number of generations.
CADENCE PIZZA PARTY
(Monday August 19, 6:30 - 7:30 PM)
SPONSORED BY CADENCE DESIGN SYSTEMS
, San Jose, California, USA
MP 3.1 7:30 - 9:30 pm Panel Discussion - Scheman Benton Auditorium
Industrial CAD Tools in Academe
Moderator: John Choma, Jr., University of Southern California
Panelists:
Kent Leung, Cadence Design Systems
Richard E. Oettel, Cascade Design Automation
Joseph Hance, Mentor Graphics Corporation
Dennis Boylan, Analogy Incorporated
Jeffery Echtenkamp, Rockwell International
Magdy Bayoumi, University of Southwestern Louisiana
Elizabeth Brauer, University of Kentucky
The panel consists of two groups. The first group represents leading CAD tool companies with prominent university programs. Each company representative will present a short summary of their university program. The second group represents the university users' community. Each university representative will present a short summary of his/her experiences with various tools usage and support. The panel will then be open for what promises to be a very stimulating and challenging discussion with the audience.