1996 Midwest Symposium on Circuits and Systems
August 18-21, 1996
7:30 am - 6:00 pm Registration Desk Open - Scheman First Floor
Lobby
7:30 - 8:30 am Continental Breakfast - Scheman First Lobby
8:30 - 10:00 am CONCURRENT SESSIONS
TA1.1 Logic Circuit Design - Sankaran Menon, Chairperson - Scheman Room
167
Low Power Circuit Techniques for Fast Carry-Skip Adders
Eric S. Gayles, Robert M. Owens, Mary Jane Irwin, The Pennsylvania State
University, state College, Pennsylvania, USA
A multi-level carry-skip addition scheme for static CMOS is presented which
has O(lg n) asymptotic delay and has speed comparable to a carry-lookahead
for typical operand bit precisions. However, the proposed architecture results
in adders which dissipate nearly half the power of carry-lookahead adders.
The proposed carry-skip method is also conflict free. This paper describes
the proposed architecture and its circuit implementation, as well as the
architecture's asymptotic worst case delay analysis. Also, empirical results
comparing the adder's performance with other conventional architec tures
in a 0.5 micron CMOS process are provided.
A Fast Optimal CMOS Full Adder
A.T.M. Shafiqul Khalid, Ascent Solutions Inc., Miamisburg, Ohio, USA
Two CMOS full adders have been developed in this paper based on the transmission
function theory. Proposed adders are comparable to conventional design in
terms of number of gates. The design also gives better operational speed
over Zhuang-Wu design. HSPICE simulation proves the functionality of the
design.
New Ternary and Quaternary Voltage-Mode CMOS Inverter Implementations
Srinivasa R. Vemuru, Guosen Luo, City College of New York, New York,
New York, USA
Multiple-valed logic can be used to overcome interconnect and I/O pin count
bottlenecks in integrated circuit designs. New voltage-mode implementations
of ternary and quaternary inverter circuits are presented. These all MOS
transistor circuits use a single supply voltage and can be implemented in
a standard CMOS process.
Improved Low-Voltage Dynamic BiCMOS Logic Gates Using Output Feedthrough
S. M. Rezaul Hasan, Universiti Sains Malaysia, Malaysia; Chakaravarty
Rajagopal, Intel Penang VLSI Design Center, Penang, Malaysia; Nazmul Ula,
Loyola Marymount University, Los Angeles, California
An improvement to the recently proposed BiCMOS dynamic gates is presented.
The well-known "MOS clock feedthrough effect" is used to achieve
full swing with substantially reduced low-to-high transition delay. This
improved design allows the BiCMOS dynamic gate to operate down to 1.5V supply
voltage, and hence, makes it suitable for advanced deep sub-quarter-micron
BiCMOS technolo gies with considerably scaled down power supplies.
TA1.2 Simulation and Acceleration - Jay Brockman, Chairperson
- Scheman Room 262
Krylov Subspace Based Model-Order Reduction Techniques for Circuit
Simulations
Wendemagegnehu T. Beyene, Jose E. Schutt-Aine, University of Illinois
at U-C, Urbana, Illionis, USA
Recently, asymptotic waveform evaluation technique and its derivatives based
on moment-matching methods have been used for efficient analysis of linear
networks. In this paper, techniques based on Krylov-subspace methods are
presented for generating reduced-order models of large linear networks in
a computationally efficient manner. An optimum reduction technique is applied
for distributed systems to drive higher-order finite models as an intermediate
stage in order to obtain lower-order models. The method can be used for
time and frequency response approximations of large networks. Illustrative
examples are also given to study the computational efficiency and accuracy
of the method.
Acceleration of Analog Simulation by Partial LU Decomposition
Albert Davis, Lucent Technologies, Allentown, Pennsylvania, USA
This paper presents a method for accelerating analog simulation by incrementally
updating the admittance matrix, and re-solving only the part of the matrix
that depends on the factors that changed. There is substantial speedup for
large linear subcircuits, such as interconnect, and large digital circuits
exploiting latency.
A Visual Simulation Environment for Efficient Characterization of Analog
Circuit Behavior
M. Goedecke, S. Huss, Technische Hochschule Darmstadt, Darmstadt, Germany
This paper presents a new approach to the characterization of analog circuits
based on the visual programming paradigm. An enhanced data-flow language
acts as the central specification means for characterization tasks. A data-flow
scheduler for a distributed environment is proposed, which provides parallel
simulation services without any user interaction. The advantages of this
simulation environment are demonstrated for a complex characterization task
of a nonlinear circuit.
Model Reduction Technique for Structured Linear Uncertain Systems
J.M. Jahabar, Indian Institute of technology, Bombay, India
This paper presents a method for reducing the high order structured linear
uncertain system described by differential equation, with a set of specified
initial conditions, to a lower order one. The coefficients of the reduced
model are obtained by matching the integral of the square of the output
and its first r - 1 derivatives of the reduced model with that of
the original structured linear uncertain system. A numerical example illustrates
the procedure.
TA1.3 Neural Network Implementations I - Shreekanth Mandayam, Chairperson
- Scheman Room 260
A Voltage Based Winner-Take-All Circuit for Analog Neural Networks
Janusz A. Starzyk, Ying-Wei Jan, Ohio University, Athens, Ohio, USA
This paper presents a voltage based winner-take-all (WTA) circuit. The WTA
circuit is based on a NMOS winner follower and CMOS differential amplifiers.
The voltage based design uses capacitive storage for lower power consumption.
The WTA is accelerated by employing cascaded differential amplifier. Modular
design makes the proposed WTA circuit suitable for VLSI implementation.
Novel Electronic Hardware for Pulse-Mode Neural Circuits
Kenneth Roenker, C.K. Song, University of Cincinnati, Cincinnati, Ohio,
USA
A new approach to the electronic hardware implementation of pulse-mode neural
circuits is described that is not based on the use of conventional transistors,
but on a novel semiconductor device called a Multi-Quantum Well Injection
Mode Device (MQW-IMD). Described is the device's operation in simple circuits
which exhibit neural-like characteristics, i.e. pulse generation, signal
integration and synaptic weighting.
Compact VLSI Implementation of Cellular Neural Network
Ari Paasio, Adam Dawidziuk, Veikko Porra, Helsinki University of Technology,
Espoo, Finland
A very compact CNN cell has been designed. This CNN can operate on black
and white images. The designed cell is used to build up a 16 x 16 cells
network. This design has been sent to 0.8 micron CMOS process. The cell
dimensions are 114 x 118 um 2.
9x9 DPCNN Board: A Multichip Approach to CNN Implementation
Mario Salerno, Faussto Sargeni, Vincenzo Bonaiuto, University of Rome,
Rome, Italy
The paper presents a multichip 9x9 CNN board which is made up of nine 3x3DPCNN
chips. This 9x9 CNN board is fully programmable by a Personal Computer.
A software program enables the selection of the templates and the inputs,
and the steady-state voltages acquisitions. The system PC-9x9CNN board represents
a very powerful tool in the investigation on new CNN algorithms as well
as their dynamic behaviours.
TA1.4 RNS Techniques for High Performance VLSI Digital Signal Processing
I
William Chren Jr., Hoda S. Abdel-Aty-Zohdy, Chairpersons
Hoda S. Abdel-Aty-Zohdy, William Chren Jr., Session Organizers - Scheman
Room 252
An RNS Implementation of Real Orthogonal Transforms via Approximations
over a Direct Product of Quadratic Number Fields
V.S. Dimitrov, G.A. Jullien, W.C. Miller, University of Windsor, Windsor,
Ontario, Canada
This paper continues the exploration of the original Cozzens and Finklestein
idea of combining the algebraic integer quantization of integer data with
an inner parallelism provided by an RNS represen tation. Our application
is in the area of real-valued transform computation. We propose an approxi
mation scheme using a data representation as pairs of integers. The error
of the approximation can be made arbitrarily small, with subsequent processing
steps error-free. Our algorithm is based on an irrational number system,
which might be viewed as a generalization of the irrational arithmetic proposed
by Bergman. Using a suitable quadratic field, over which we perform the
calculations, we are able to reach a sufficiently large dynamic range using
fairly small moduli. We show that when 6-bit moduli are allowed, the computation
corresponds to dynamic ranges in excess of 27-bits.
Digital Signal Processing with Serial-by-Modulus Residue Arithmetic
W.K. Jenkins, R. Liu, University of Illinois at U-C, Urbana, Illinois,
USA
This paper proposes two processor designs where digit-serial RNS arithmetic
is attractive in DSP: i) variable word-length DSP, and ii) "compute-until-correct"
fault tolerant DSP. In both designs just enough error-free RNS digits are
computed to satisfy instantaneous dynamic range requirements, although the
capability is provided to compute additional RNS digits upon demand.
Combinational Logic Design Approach of a Residue-Arithmetic Multiplier
Ahmad Hiasat, Princess Sumaya University, Aman, Jordan; Hoda S. Abdel-Aty-Zohdy,
Oakland University, Rochester, Michigan, USA
In this paper, we introduce a new design approach for residue arithmetic
number system multiplica tion. This design uses combinational logic. Forming
a truth table of 2n input bits, where the first n bits are the bits of the
multiplier and the other n bits are bits of the multiplicand, the output
is shown to require n bits. Since the modulus m is less than 2^n , then
a total of (2^(2n) - n^2) don't care cases occur in the truth table. Therefore,
minimizing the truth table would result in fewer number of minterms, and
consequently, simpler sum-of-products form for implementing modular multiplication.
Compared to ROM and other customized approaches for realizing residue multipliers,
this approach requires less than half the number of gates.
Delay-Power Product Simulation Results for One-Hot Residue Number System
Arithmetic Circuit
W.A. Chren Jr., C.H. Brogdon, Grand Valley State University, Grand Rapids,
Michigan, USA
We present Spice simulations which verify previous analytical estimates
of the delay-power product of One-Hot Residue adders and multipliers. These
simulations show a 75% reduction in the product below binary adders and
an order of magnitude reduction for multipliers. From these results, analyti
cal models are derived and used to predict performance for larger moduli.
Finally, low-area adders and multipliers for large moduli are presented.
TA1.5 Communications I - Jungwhan Kim, Chairperson - Scheman Room
275
A Robust Self-Adaptive Approach for Multiple-Access Interference
Suppression
Sang C. Park, John f. Doherty, Iowa State University, Ames, Iowa, USA
We present a robust self-adaptive algorithm for DS/CDMA interference suppression.
The algorithm adjusts the filter coefficients by minimizing a non-MSE cost
function while satisfying a set of con straints. Performance sensitivity
of the reference-free constrained algorithm is studied. The algorithm significantly
improves steady state performance compared to existing adaptive algorithms.
An Interference Cancellation System for Spread Spectrum Communication
Channels with Cochannel FM Interferers
David Rich, Lucent Technologies, Whitehall, Pennsylvania, USA; M.H. Kermalli,
F.A. Cassara, J.J. Benson, Polytechnic University, Farmingdale, New York,
USA
This paper examines the mutual interference that exists when broadband direct
sequence spectrum signals and narrowband FM users are overlaid in the same
frequency band. The paper also examines the ability of a novel adaptive
tracking notch filter placed at the front end of the spread spectrum receiver
to suppress strong co-channel narrowband FM users.
A Novel Approach to the Design and Enumeration of Bode-Type Variable-Amplitude
Digital Equalizers
Arthur T.G. Fuller, Behrouz Nowrouzian, The University of Calgary, Calgary,
Alberta, Canada
This paper presents a novel approach to the design and enumeration of Bode-type
variable-amplitude digital equalizers. A set of realizability conditions
are developed for the design of such digital equaliz ers having arbitrary
shaping transfer functions. The relationship between the range of variable
multiplier variation and the resulting range of logarithmic magnitude-frequency
response variation of the equalizer is discussed. The results thus obtained
are applied to the design and enumeration of a class of 51 bump digital
equalizers (one of which was reported in the literature some time ago).
TA1.6 Data Converters II - Ramesh Harjani, Chairperson - Scheman
Room 250
Adaptive Equalization of Channel Gain Mismatches in pDS ADC
Shyang K. Kong, Walter H. Ku, University of California at San Diego,
La jolla, California, USA
pDS ADC architecture, proposed by Professor Ian Galton, does not require
time oversampling. However, gain mismatches among the channels will limit
the performances of this architecture. We propose an adaptive scheme may
be used to equalize the channel gain to improve the performance of this
architecture.
A High Resolution Two-Stage S-D ADC Based on a New Calibration Method
Adnan Harb, Mohamad Sawan, Ecole Polytechnique de Montreal, Montreal,
Quebec, Canada; Baher Haroun, Texas Instruments, Dallas, Texas, USA
This paper describes a new high resolution Analog-to-Digital Converter (ADC)
dedicated to implant able biomedical sensors. The ADC is based on a two
stage oversampling sigma-delta architecture. The three main features of
the proposed ADC are high resolution, low area and reduced energy consumption.
An adaptive algorithm is employed to optimize the above mentioned parameters.
It allows the calibration of the components mismatching and the internal
employed Digital-to-Analog Converter (DAC). The simulations show that the
proposed converter reaches an 18 bits resolution for a 25 kHz bandwidth
running at a 1.6 MHz oversampling frequency.
Frequency Doman Analysis of pDS ADC and Its Application to Combining
Subband Decomposition and pDS ADC
Shyang K. Kong, Walter H. Ku, University of California at San Diego,
La Jolla, California, USA
Parallel Delta Sigma ADC architecture, proposed by Professor Ian Galton,
does not require time oversampling. Frequency domain analysis shows that
this architecture is closely related to the subband decomposition based
ADC. Furthermore, parallel delta sigma ADC can be combined with subband
decomposition based ADC in a straight forward manner.
A Two-Stage Sixth-Order S-D ADC with 16-Bit Resolution Designed for an
Oversampling Ratio of 16
Alan J. Davis, Naval Undersea Warfare Center, Newport, Rhode Island,
USA; Godi fischer, University of Rhode Island, Kingston, Rhode Island, USA
This paper presents a sixth-order sigma-delta modulator capable of 16 bit
resolution with an oversampling ratio (OSR) of only 16. The circuit's sensitivity
to non-idealities such as amplifier finite open-loop gain, bandwidth and
slew rate or capacitor mismatches is minimized through the use of a novel
topology. Efficient noise shaping is realized by cascading two nearly identical
third-order modulators. The dynamic range is maximized by placing a finite
zero in the noise shaping function of each modulator loop. The resolution
is further enhanced through the use of ternary quantizers which halve the
quantization noise while avoiding the linearity problems associated with
higher resolution DACs required in the modulator feedback paths. The presented
modulator has been fabricated as a fully-differential switched-capacitor
circuit by a 1.2 um double-poly CMOS process and operates from a 2.5 volt
power supply.
A Forward Successive Approximation A/D Converter Architecture
N. Hamdy, Arab Academy for Science & Technology, Alexandria, Egypt;
H. Soliman, Mansoura University, Mansoura, Egypt
A successive-approximation quantization technique in a parallel architecture
is presented. Forward determination of the non-zero bits in an n-bit word
is achieved using n-parallel-connected compara tors, n-EX-OR's and a D/A
converter over n cycles. An R-2R resistor ladder network is used to develop
reference voltages for the comparators. The technique allows direct cascading
of identical stages and is amenable for monolithic fabrication.
TA1.7 Nonlinear Systems - Paul Furth, Chairperson - Scheman Room
208
Identification of Nonlinear Systems with Evolving Networks
Richard A. Wasniowski, Sandia Research Center, Albuquerque, New Mexico,
USA
This paper discusses the practical aspects of developing parallel algorithms
for nonlinear systems identification using evolving networks. It shows how
computation intensive identification problems can be modeled on parallel-like
simulators and computed efficiently on networks of workstations. A unified
framework within which large parallel identification programs can be developed
on a collection of heterogeneous machines is introduced in order to make
easy transition from sequential processing into parallel processing.
A Comparative Study of Non-Linear System Identification Using Parallel
Cascades C.S. Zhao, Queen's University, Kingston, Ontario, Canada;
M. Farooq, Royal Military College of Canada, Kingston, Ontario, Canada;
M.M. Bayoumi, Queen's University, Kingston, Ontario, Canada
A discrete time non-linear system can be uniformly approximated to an arbitrary
degree of accuracy by a sum of sufficient number of parallel cascades. In
this paper, we use both the polynomial func tions and a set of gate functions
to represent the non-linearity in each cascade. We found that a gate function
implementation works better than a polynomial implementation at the initial
stages and the polynomial implementation performs well for the the output
corrupted with noise. Based on these observations, we have used a hybrid
structure for a non-linear system identification, adopting the gate function
techique for the initial several cascade paths followed by the polynomial
approach. Simulation results show that this hybrid structure substantially
reduces the mean-square error.
A Multivariable PI Controller for Nonlinear Ill-Conditioned Electrical
Tubular Ovens
José Maria Gálvez, Lauzier Pereira de Araujo, Federal University
of Minas Gerais, Belo Horizonte, M.G., Brazil
The control of multivariable systems has been a wide area for investigation
of new methods and techniques. One of the primary objectives of the control
design problem is to overcome the usually existent cross-coupling between
inputs and outputs which obscures the effects of a specific loop controller
on the system behavior. In the case of temperature control the problem is
still more chal lenging due to the time delays and nonlinearities involved
in the process. This paper considers the application of frequency domain
techniques to the design of multivariable feedback controllers for nonlinear,
multiple-heating-zones, electrical oven systems. Multivariable frequency
domain tech niques are used to analyze the system, to improve the system
decoupling and to validate a single -input single-output (SISO) linear control
design approach. Simulation results are presented.
Unstable Periodic Orbit and Aperiodic Orbit Stablilization in Chaotic
Systems by Input -Output Linearization
L. Fortuna, University of Catania, Catania, Italy; C.Vinci, Fuzzy Logic
R&D Group, SGS-THOMSON Microelectronics, Catania, Italy
Results on chaos control solved via Input-Output Linearization are presented.
Evidence of the achieve ment of stabilization to unstable periodic orbits
or aperiodic orbits extracted from its own attractor is given for a representative
Chua's unfolded chaotic system, for different sets of parameters values
and also in case of parameters variations. These results shows effectiveness
of the Feedback Linearization as a methodology for both stability analysis
and control design for chaotic systems.
TA1.8 Transmission Lines - Robert Weber, Chairperson - Scheman
Room 204
Formulation of the Klopfenstein Tapered Line Analysis from Generalized
Nonuniform Line Theory
Ghader Razmafrouz, University of California, Davis, California, USA
The objective of this problem is to formulate the Klopfenstein analysis
of the nonuniform line in the generalized integral equation format. The
integral equation approach to the analysis of a nonuniform microstrip line
is a general approach which gives the equation for reflection coefficient
of any tapered line without optimization. In this paper, the aim is to examine
the general formulation of Youla, and derive Klopfenstein's result for the
optimum reflection coefficient of the line.
Application of Volterra Series in Modeling Human Systemic Arteries Simulated
on PSPICE
Harry C. Gundrum, Maher E. Rizkalla, Akhouri S.C. Sinha, Purdue University
at Indianapolis, Indianapolis, Indiana, USA
The Volterra Series is used for the transient analysis of linear lumped
elements in lossy coupled transmission line with mildly nonlinear terminations.
This method is also applied to modeling wavefronts of electrical signals
representing blood pressure and flow in human arterial systems which has
been modeled as a very nonlinear transmission line. PSPICE is used to simulate
the transient response.
Simulation of Intermodulation Generation and Propagation Along Nonlinear
Transmission Lines
Xuegang Zeng, Thomas Wong, Illinois Institute of Technology, Chicago,
Illinois, USA
The frequency-domain intermodulation-balance (FDIB) is applied to simulation
of intermodulation generation and propagation along nonlinear transmission
lines with two-tone inputs, and compared with the standard two-tone harmonic-balance
technique. One of the advantages is a higher computational efficiency with
respect to other techniques.
Micromachined Microwave Transmission Lines by Commercial CMOS Fabrication
Veljko Milanovic, The George Washington University, Washington, DC,
USA; Michael Gaitan, Edwin D. Bowen, National Institute of Standards and
Technology, Gaithersburg, Maryland, USA; Mona E. Zaghloul, The George Washington
University, Washington, DC, USA
The paper reports fabrication of coplanar waveguides through commercial
CMOS foundry with additional maskless etching. Transmission lines were fabricated
through MOSIS, and subsequently suspended by surface etching. Absence of
silicon substrate results in significantly improved insertion loss characteristics,
dispersion characteristics, and phase velocity. Measurements from 100 MHz
to 20 Ghz show orders of magnitude improvement of loss characteristics.
TA1.10 CAD and Modeling for VLSI - Sachin Sapatnekar, Richard Meitzler,
Chairpersons
- Scheman Room 171 - 179
A Circuit Extractor Based on a Novel Method to Represent Layout Regions
J.M.S. Alcantara, C.E.T. Oliveira, M.L Anido, Universidade Federal do
Rio de Janeiro, Rio de Janeiro, R.J., Brasil
This paper presents a novel circuit extraction tool using a data structure
based on maximally-horizon tal layout regions termed X-spans and on contiguous
vertical regions termed Y-spans. The paper also discusses the characteristics
required by the extractor structure to properly support the required tasks
such as the numeration of nodes and the extraction of transistors. Most
of the primitive operations which are necessary to support a circuit extractor
based on a layout representation using X and Y sapans are presented and
special attention is paid to the solution of the difficult problem of consolidating
the node table.
Efficient Layout Editing by Combining Disk Storage Layout Partitioning
and Cell Hierar chies
M.L. Anido, C.E.T. Oliveira, Universidade Federal do Rio de Janeiro,
Rio de Janeiro , R.J., Brasil
This paper presents an efficient solution to the problem of dealing with
the layout description of very large chips represented by large CIF 2.0
files, and discusses how this solution is matched with the philosophy of
using cell hierarchies on a VLSI layout editor. The main objectives are
achieving faster disk access and attaining lower memory demands to be able
to perform layout editing efficiently. This paper also presents the algorithms
required to implement the functions that deal with cell hierarchies and
cell instances in a hierarchical layout editor and also discusses several
problems related to cell hierarchies and cell instances.
An Efficient Interior Point Approach for QP and LP Models of the Relative
Placement Problem
Andrew A. Kennings, Anthony Vannelli, University of Waterloo, Waterloo,
Ontario, Canada
Cell placement can be performed using a combination of mathematical programming,
graph partitioning and iterative improvement techniques. Mathematical programming
provides the relative positions of cells throughout the placement area while
ignoring several placement restrictions. We describe quadratic and linear
program formulations for finding relative cell positions. Moreover, we demonstrate
that both formulations can be solved using an interior point method. Numerical
results are presented to demonstrate the effectiveness of the formulations
and the solution methodology.
Multi-Objective Based Placement for Custom Macro-Cells
Ousmane Diallo, Lori Lucke, Univesity of Minnesota, Minneapolis, Minnesota,
USA
In the VLSI macro-cell placement problem routing areas are typically included
within the macro-cells. We present a genetic solver for the placement problem
where the routing area is considered sepa rately from the cell area. This
allows us to explicitly account for power dissipation. We demonstrate efficient
placements in short cpu times.
Genetic Algorithm for VLSI Channel Routing in the Presence of Cyclic
Vertical Constraints
Anthony D. Johnson, The University of Toledo, Toledo, Ohio, USA; Rongchun
Sun, Intel
Corporation, Folsom, California, USA
The first genetic router for Manhattan model channels which contain cyclic
vertical constraints has been implemented. It creates an initial population
without violations of constraints using the theory of locally optimal breaking
of cyclic vertical constraints. A new encoding scheme, and a new mutation
operator are introduced.
A New CFA Frequency Model Including Load-Dependent Unstabilities
Eduard Alarcon, Artur Frigola, Eva Vidal, Alberto Poveda, Universitat
Politecnica De Catalua, Barcelona, Spain
The current-feedback operational amplifier (CFA) is an active device which
uses the supply-current sensing technique in order to achievehigh performance
features for analog signal processing applica tions. However, under certain
load conditions the CFA exhibits an unstable behaviour. This work presents
a new frequency model which takes into account the non-unilateral characteristics
of the CFA buffer stages and predicts the load-dependent unstabilities.
The model can be easily incorpo rated into a standard macromodel for simulation
purposes or used analitically for accurate circuit design based on CFAs.
As a consequence of this approach, some improvements in the CFA structure
could be suggested.
A Complete OTA Frequency Model
E. Alarcon, A. Poveda, E. Vidal, Universitat Politecnica De Catalunya,
Barcelona, Spain
A complete model for the Operational Transconductance Amplifier (OTA) is
presented. The model includes the transconductance frequency response, the
input bias current to output current transfer function, as well as the dependence
of both input and output impedances on input bias current. This model is
suitable for being included in complex simulation macromodels or used in
analytical calcula tions. Simulation results and comparisons are also presented.
Automatic Switching Synchronization of Serial and Parallel Avalanche
Transistors Connec tion
Sergey Naumovich Vainshtein, A.F. Ioffe Institue, St. Petersburg, Russia;
Juha Tapio Kostamovaara, Risto Antero Myllyla, University of Oulu, Oulu,
Finland
150 A / 10 ns current pulses across a low - ohmic resistive load ( 1 Ohm
) were obtained using Marx -type serial connection of the stages with parallel
connection of a few avalanche transistors in each stage. The automatic feedback
allows perfect time synchronization of the switching process in all the
transistors.
A Survey of Public-Domain and Shareware Programs Useful to EE Students
- Part II
R. Eugene Stuffle, Idaho State University, Pocatello, Idaho, USA
This paper presents the results of an ongoing survey of public-domain and
shareware programs useful in electrical engineering education. Brief discussions
of those we feel are simultaneously sufficient for classwork applications
and reasonable in cost are presented. Sources for all programs discussed
will be provided.
A Netlist Verification Algorithm of Regular VLSI Structures
Alexander Y. Tetelbaum, Michigan State University, East Lansing, Michigan
The paper considers the problem of testing for the isomorphism of graph/hypergraph
models of subsystems such as memories, regular electronic structures, networks,
and connection machines that are homogeneous graphs with possibly automorphic
subgraphs. Using the efficient algorithms for non-homogeneous graphs for
this class of system can lead to exponential running time. To resolve this
situation, an efficient and accurate algorithm is presented.
10:00 - 10:30 am Refreshment Break - Scheman First Floor Lobby
10:30 - 12:00 pm CONCURRENT SESSIONS
TA2.1 VLSI for Digital Signal Processing - Devinder Kaur, Chairperson
- Scheman Room 167
Fast Sampled-Data Wavelet Transform CMOS VLSI Implementation
Gerardo Gonzalez-Altamirano, Jaime Ramirez-Angulo, New Mexico State University,
Las Cruces, New Mexico, USA; Alejandro Diaz-Sanchez, Centro Nacional de
Investigacion y Desarrollo Technologico, Cuernavaca, Mexico
This paper presents the VLSI CMOS implementation for a one-dimensional Fast
Sampled-Data Wavelet Transform (FSDWT) circuit as well as its inverse based
on subband dyadic decomposition using quadrature mirror filter banks (QMF).
The novelty of this approach lies in the use of analog tapped delay lines,
analog four-quadrant multipliers, and current addition in order to build
the analysis and synthesis stages of a programmable QMF. This paper presents
basic architecture, as well as transistor level computer simulations. Important
VLSI features for this approach are the following: area efficiency, high
speed, and low power consumption.
VLSI Implementation of High Speed Digital Filters Using Direct Form Structures
Markku Eraluoto, Juha Kauraniemi, Iiro Hartimo, Helsinki University of
Technology, Espoo, Finland
VLSI implementation of high speed delta operator realized digital filters
has been studied. An example filter was implemented using the approach described
in this paper. It is shown that the use of the delta operator in narrowband
filtering applications can result in up to 40 % saving in hardware resources
compared to conventional delay realizations with equal roundoff noise performance.
A Multiplier and Squarer Generator for High Performance DSP Applications
Johnny Pihl, Norwegian University of Science and Technology, Trondheim,
Norway
A generator for multiplier and squarer structures, suitable for high performance
bit-parallel DSP applications in VLSI, is presented. The squarer structure
employs a novel bit-parallel partial product reduction scheme, reducing
delay and hardware by 50%, compared to a full multiplication. The generator
is based on optimized Wallace trees, Booth encoding and binary tree vector
merging addition. Computation of weighted square sums is used as a design
example, which has applications in e.g. pattern recognition. Examples are
given for in a standard 0.8mu CMOS process.
A Unified VLSI Architecture for Decomposition and Synthesis of Discrete
Wavelet Trans form
Ming-Hwa Sheu, Ming-Der Shieh, Shuehn-Fa Cheng, National Yunlin Institute
of Technology, Touliu, Yunlin, Taiwan
This paper presents a unified VLSI architecture that can perform the decomposition
and synthesis of Discrete Wavelet Transform (DWT). This architecture comprises
the characteristics of no multiplier, shorter latency and higher throughput
rate, and using the same circuit without modification for decomposition
and synthesis of DWT.
TA2.2 Structural and Programmable Design - Elizabeth J. Brauer, Chairperson
- Scheman Room 262
An FPGA-Based Hardware Emulator for Fast Fault Emulation
Jin-Hua Hong, Shih-Arn Hwang, Cheng-Wen Wu, National Tsing Hua University,
Hsinchu, Taiwan
An FPGA-based hardware emulation system is shown to boost the speed of fault
simulation for sequential circuits. Fault injection is made easy by shifting
the content of a fault injection chain, without the highly time-consuming
bit-stream regeneration process. Experimental results for ISCAS -89 benchmark
circuits show that the fault emulator is about twenty times faster than
HOPE.
Diffusion Sharing Across Cell Boundaries in Cell Based Design
Bharat Krishna, Naresh K. Sehgal, Intel Corporation, Santa Clara, California,
USA; C.Y. Roger Chen, Syracuse University, Syracuse, New York, USA
A layout design often contains regular, repeatable or iterative structures,
and datapath is an example of such a design-style. Designers take advantage
of regularity by using library cells for density and productivity improvements.
This study is aimed at studying the impact on overall density due to diffusion
sharing across cell boundaries. Often the library cell area is optimized
without comparing the global impact on the assembled design. We compare
two methods of designing cells, a practically used one and an intuitively
desired one. We show that the intuitive method is not always feasible and
that a hybrid method of designing a cell is optimal. Studies on real examples
have shown the gains to be made in density by diffusion sharing across cell
boundaries. We also present situations in which the diffusion sharing causes
a loss of overall density. The conclusion will be a set of guidelines on
when to use diffusion sharing among the library cells.
Optimized Embedding of Incomplete Binary Tree to Two-Dimensional Array
of Program mable Logic Blocks
Malgorzata Chrzanowska-Jeske, Yang Xu, Portland State University, Portland,
Oregon, USA
An efficient scheme for embedding an incomplete binary tree, representing
a combinational circuit, in a two-dimensional array of programmable logic
blocks is presented. This problem appears in layout-driven logic synthesis
for combinational circuits which are implemented with fine-grain Field Programmable
Gate Arrays. An efficient data structure and node sorting algorithm are
used to restructure the binary tree. During mapping of the restructured
tree no routing blocks are inserted into the longest paths, and the area
occupied by the mapped tree is minimized. No routing is neces sary, and
only the assignment of primary variables to local busses is performed. A
comparison between previuous methods and ours is shown using the ATMEL6000
FPGA series as a target architectures.
A Topology-Based Multi-Way Circuit Partition for ASIC Prototyping
Yhonkyong Choi, Chong S. Rim, Sogang University, Seoul, Korea; Young
Sook Jeong, Electronics Telecommunications Research Institute, Taejon, Korea
A new circuit partition problem is described for programmable circuit boards
in which the routing topology among chips are predetermined. An efficient
simmulated annealing based partition method enhanced by tree clustering
techniques is described for the problem. Experimental results for several
circuits show that the method gives very good solutions.
TA2.3 Neural Network Implementations II - Tim Holman, Chairperson
- Scheman Room 260
High Speed Digital VLSI Fuzzifier
Jaime Ramirez-Angulo, New Mexico State University, Las Cruces, New Mexico,
USA; Jorge Zrilic, New Mexico Highlands University, Las Vegas, New Mexico,
USA; Gabriel Escarpita-Monarrez, Anabell Beltran, Universidad Autonoma de
Ciudad, Juarez, Mexico
A digital high speed VLSI fuzzifier is introduced. It is a very compact
system characterized by a trapezoidal shaped membership function which is
defined in terms of four programmable param eters. It performs fuzzification
in ~30nS. Utilization of this circuit in a multiplexed fashion for simple
implementation of rule inference engines and defuzzification schemes are
discussed.
VLSI Design for a Forward Path Neuron Circuitry of a Back Propagation
Neural Network
Richard L. Aldridge, Maher E. Rizkalla, Mohamed El-Sharkawy, Indiana
University Purdue University Indianapolis, Indianapolis, Indiana, USA
This paper describes the hardware required to implement a back-propagation
neural network on a VLSI chip utilizing 2 -CMOS technology without modifications
to the algorithm. The SPICE simulation results for the forward path consisting
of transconductance amplifiers, summer weighted circuits, and the sigmoid
functions are presented, and the experimental verifications are included.
A Pulse-Stream Neuron With Sigmoidal Transfer Characteristic
R.J. Haycock, T.A. York, UMIST, Manchester, England
A novel circuit is described that produces a sigmoidal neuron transfer function
for a pulse-stream neural network. The input activation is represented by
a voltage and the output by the time between pulses. The circuit employs
BiCMOS technology and utilises 17 MOSFETs, 2 bipolar transistor and 2 capacitors.
A New Multiplierless Digital Synapse with Parallel Data Addressing
In-Jung Park, Dankook University, Choong-Nam, Korea
In the hardware implementation of neural network, the method of signal processing
will be divided into tow, digital or an analog one. The analog method have
high fabrication and fast computing. But there are many problems of which
are saving of signal, nolinearity of multiplier, access of preci sion, zero
offset, noise, gain, and so on. The digital method have some advantages
such as easy change of precision, saving of data, connecting and multiplexing
of signal, easy design of circuit, easy connecting of chips.
TA2.4 RNS Techniques for High Performance VLSI Digital Signal Processing
II -
William Chren Jr., Hoda S. Abdel-Aty-Zohdy, Chairpersons
Hoda S. Abdel-Aty-Zohdy, William Chren Jr., Session Organizers - Scheman
Room 252
RSA Decryption Using the One-Hot Residue Number System
W.A. Chren Jr., Grand Valley State University, Grand Rapids, Michigan,
USA
This paper presents an RSA decryption circuit based on the One-Hot Residue
number system. The design exemplifies the superior delay-power product performance
of the number system when applied to a computationally intensive application.
Low-area alternatives to the standard barrel shifter architectures for large
moduli are also presented.
A Novel Fault Tolerant RNS Processor
D. Radhakrishnan, A.B. Premkumar, Ang Ee. Luang, Nanyang Technological
University, Singapore
The advantages of 2n+1 moduli set are lost if two redundant moduli with
similar properties are chosen for fault tolerance. In order to overcome
this difficulty and at the same time to meet the constraints required for
fault tolerance, we propose to add an additional smaller modulus without
unduly increasing overall complexity of the hardware.
Fixed Point Fractional Representation in Residue Number System
Andraos Sweidan, University of Jordan, Amman, Jordan
Representing fractions is one of the fundamental problems in Residue Number
System (RNS) which is considered an integer number system with no fractional
representation. This is one of its drawbacks. In this paper, a method for
representing fractions in RNS is developed. The addition of fractions is
easily implemented using this method. The multiplication operation is also
implementable, but with more sophisticated procedure. The choice of the
way to represent a fraction in accordance with the new method is determined
using two criteria: the Uniqueness Criterion and the Precesion Criterion.
Real numbers representation is also introduced and analyzed. The general
equation for real number multiplication, which is the most difficult one,
is introduced.
TA2.5 Communications II - Junghwan Kim, Chairperson - Scheman
Room 275
Blind Equalization for 16 - QAM
Junghwan Kim, C.Y. Yang, The University of Toledo, Toledo, Ohio, USA
A new blind equalization algorithm is proposed. The advantages are the lower
residual error and faster convergence property. The performance of the algorithm
is illustrated using 16-QAM signal constellation. Computer simulation results
under fading channel demonstrates the relative superiority over the conventional
GA and Sign-GA with smaller mean square error and less number of iterations.
Analysis of Interference Cancellation Using Adaptive Notch Filters for
Multiple Interferers
David A. Rich, Lucent Technologies, Whitehall, Pennsylvania, USA;
Frank A. Cassara, Steven Bo, Polytechnic University, farmingdale, New York,
USA
This paper describes the analysis and design of an interference cancellation
system employing adaptive tracking notch filters useful for canceling multiple
cochannel FM interferers. The interference canceler is capable of separating
and frequency demodulating all the interferers even for the case when they
are cochannel and share the same frequency band.
An Optimization Model of a Combined Satellite and Terrestrial Communication
Network
M. Alam, The University of Toledo, Toledo, Ohio, USA
This paper presents a methodolgy for optimizing the topology of a combined
terrestrial and satellite communication network. There are three choices
of media for establishing a connection between any pair of nodes: satellites,
trunks, and WATs circuits. Any combination of circuits may be used for carrying
the traffic between any pair of nodes. The problem is transformed into a
non-linear program ming problem with stochastic constraints. An algorithm
for solution is developed by constructing a simulation model of the communication
network using SLAM simulation language.
Performance Characteristics of the IS-95 Standard for CDMA Spread Spectrum
Mobile Communication Systems
Vijayalakshmi R. Raveendran, John F. Doherty, Iowa State University,
Ames, Iowa, USA
A new software simulation methodology to implement a mobile communication
system based on the IS-95 CDMA Spread Spectrum standard is developed using
the dynamic system simulation toolbox SIMULINK(R), in MATLAB(R). Simulation
mode is of information sources, baseband process ing, QPSK modulator, measurement-based
multipath fading and RAKE demodulator are used in system-level performance
evaluation. An optimum combining RAKE receiver with considerable performance
improvement over four-way combining is also proposed in this paper.
TA2.6 Analog Filters I - John Choma Jr., Chairperson - Scheman
Room 250
Generation of Current Mode Filter Structures Using Dual Output Transconductance
Ampli fiers
Mansour Moniri, Bashir Al-Hashimi, Staffordshire University, Stafford,
United Kingdom
A general procedure for generating filter structures based on dual output
operational transconductance amplifiers (OTA) is presented. A structural
approach is employed to determine the capability of dual output OTAs to
realise transfer functions of various filter responses. This paper discusses
the generation of useful second order filter configurations including lowpass,
highpass, band pass and band reject responses.
Experimental Bipolar Realization of a Switched-Current Filter
Antonio Carlos M. de Queiroz, Ricardo Rhomberg Martins, Universidade
Federal do Rio de Janeiro, R.J., Brazil
The paper describes techniques for the experimental construction of switched-current
circuits, using discrete bipolar transistors and passive components. The
techniques developed are useful as a mean for "breadboard" testing
of new structures and examination of effects of nonidealities. The bipolar
design can be also used in fully integrated BiCMOS realizations, with some
the ideas having also applications in CMOS realizations, leading to wider
dynamic range and better linearity.
Low-Voltage Current-Mode Filters
Federico Galvez-Durand, CERN, PPE Division, Geneva, Switzerland
A novel current-mode filter synthesis technique is proposed based on a transformed
set of state -equations that allow the utilization of only current-mode
linear lossy-integrators, implemented using standard current mirrors; also
a novel current-mode gyrator is introduced. The technique was used for synthesizing
a low-voltage 5th order 1 MHz lowpass Chebyshev filter from a passive doubly
loaded ladder prototype. SPICE simulations using CMOS standard process level
2 parameters have shown this filter performs well, exhibiting a THD less
than 1% at 1 MHz for a 1 uA input current while the bias current per transistor
is 10 uA. Also, a Monte Carlo analysis has shown this filter preserves the
low sensitivity inherent to the passive ladder prototype. Only 22 p-MOS
transistors (plus bias) were needed. The circuit has been fed with +-1.5
V power supplies.
Current Mode Filters Using Current Conveyors
Rabindranath Nandi, Jadavpur University, Calcutta, India
TA2.7 Electronic Design Automation Tools for Industry and Education
Adam Smiarowski, Hoda S. Abdel-Aty-Zohdy, Chairpersons
Hoda S. Abdel-Aty-Zohdy, Session Organizer - Scheman Room 208
A Computer Aided Design Perspective of Advanced Logic Design
Samiha Mourad, Santa Clara University, Santa Clara, California, USA
This paper describes a novel approach to teaching an advanced logic design
course at the under graduate level. The emphasis is on the use of different
CAD tools as 1) a vehicle to accelerate the student learning of digital
design, 2) a means to demonstrate the different design approaches and implementations,
3) an instrument to measure some circuit parameters, and 4) an opportunity
to prepare the students for their careers. Course assessment through examination
results and course evaluation indicates that the CAD tools have helped clarify
and reinforce the concepts learned in the lectures and have aided the ability
the students' ability to incorporate the algorithmic nature of CAD tools
in their design process.
Set-and-See Switch-Level Simulation for VLSI Functional Verification
J.W. Smith, University of Georgia, Athens, Georgia, USA
Formulating simulator inputs for functional verification of VLSI circuits
and assessment of simulator outputs are laborious in practice. In an educational
environment, the simulator can be difficult to learn and to use. "Set-and-see"
means that while using a VLSI layout editor the designer can set the logic
values of nodes on the circuit layout interactively and see resulting node
values displayed directly on the layout.
A Comparison of Public-Domain VLSI-Chips Design Tool Suits
Hoda S. Abdel-Aty-Zohdy, Fatma A. El-Licy, Oakland University, Rochester,
Michigan, USA
Computer-Aided Design (CAD) tools play an essential role in modern microelectronics
system design. Such role become even more important as design complexity
increases and the larger the size of integrated circuit. A comparison between
two of the available CAD tool suits is presented with detailed description
of the main features and advantages. OCTTOOLS, and OASIS have been selected
as representative public domain tools for microelectronics chip designs,
using full-custom or the standard-cells semi-custom approach. An example
of six-bit multiplier is presented to illustrate quantitatively the utility
of the two VLSI design tool suits for successful design and implementation
cycle. The comparison includes: Logic and switch level simulations, placement
and routing, design verification and testability, as well as compaction.
Learning Digital Design Using Design Automation Tools
Yong Y. Li, University of Wisconsin-Platteville, Platteville, Wisconsin,
USA
This paper describes the development of using design automation tools at
the Department of Electrical Engineering, University of Wisconsin-Platteville.
A realistic design environment has been created. Students use the extensive
facilities in this laboratory to undertake the design and integra tion of
digital systems. Starting with the "Logic and Digital Design",
in four digital courses, students use schematic capture tools (Orcad, Maxplus
II, WorkView), hardware design language (AHDL, VHDL), implement EPLD, FPGA
digital devices (Altera, Xilinx). This paper describes the environment in
which the laboratory operates, the continuously support received from tool
design and chip manufacturing companies, the available equipment and the
accomplishments of the student projects during the two academic years from
September 1994 to May 1996.
Development of Board Level Simulation Models of Complex Standard Components
Hardy Pottinger, Gerard Williams, Jamie Kelly, Sandeep Tamboli, University
of Missouri Rolla, Rolla, Missouri, USA
VHDL is rapidly becoming the design language of choice for ASIC design courses
which make use of logic synthesis tools. It is often desirable to simulate
student designs embedded in a more com plete system which may be composed
of a microprocessor, RAM, ROM and other standard compo nents as well as
the student's ASIC. A bus functional model is more efficient than an equivalent
gate level model and is an attractive alternative for system level simulation.
This paper details the devel opment of bus functional VHDL models for a
system containing a digital signal processor (ADSP21020), SRAMs (IDT71024),
an FPGA used as an SBus interface (XC4013), and two FPGAs that are user
reconfigurable (XC4010). The system is a reconfigurable coprocessor board
(Chameleon Coprocessor) under development for the Sun workstation.
TA2.8 Network Analysis - Eugene Stuffle, Chairperson - Scheman
Room 204
Active Networks and Node Addition
Peichu Sheng, Peter Aronhime, University of Louisville, Louisville, Kentucky,
USA
A new node addition theorem and three corollaries applied to active networks
are presented. The purpose of this theorem is to allow modification of the
nodal admittance matrix elements of a given active network to generate new
analog circuits from existing circuitry. Two application examples of it
are provided.
Unified Nodal Analysis of Electronic Circuits
Fung-Yuel Chang, The Chinese University of Hong Kong, Shatin, New Territories,
Hong Kong
A circuit sumulator has been developed on basis of Unified Nodal Analysis.
It outperforms simulators with Modified Nodal Approach and Tableau formulation
in that the initial- and steady -state responses are generated without timing
analysis and transient simulations can be carried out even for circuits
with capacitor loops and inductor cut-sets.
Characterization of Two-Dimensional Lossless Degree One Network
Amanuel Zerzghi, Stevens Institute of Technology, Hoboken, New Jersey,
USA
A complete characterization of two-dimensional two port degree one network
has been given. This paper discusses both infinite and finite impulse responses.
The resulting characterization is implemented using lattice structures,
(Gray-Markel sections), and delays of two different types. An example using
a discretized lossless transmission line as a two port network is used to
demon strate the result.
The Application of Interchange Theorems to Linear Current-Mode Active
Networks
KeChang Wang, Peter Aronhime, University of Louisville, Louisville, Kentucky,
USA
Four theorems are provided which describe the transfer functions obtained
when the leads of any one of the nullors in a network are interchangeed
in terms of the transfer functions of the unmodified work. The network may
contain multiple nullors, multiple out- puts and multiple excitations. The
results are applied to an example network.
TA2.9 Symbolic Circuit Analysis - A. Konczykowska, Chairperson
- Scheman Room 299
Direct Symbolic Analysis of Large Analog Networks
Janusz A. Starzyk, Jun Zou, Ohio University, Athens, Ohio, USA
A new symbolic analysis approach for large analog integrated circuits is
presented in this paper. It can symbolically analyze large analog ICs without
circuit decomposition. There are no limitations for circuit topologies and
sizes. The analysis time and the memory required to store the symbolic formulas
are estimated to increase pseudo-linearly with the number of the circuit
nodes.
Efficient Determinant Evaluation in Symbolic Analysis of Large-Scale
Networks
Ben S. Rodanski, University of Technology, Sydney, Australia; Marian
Pierzchala, Hilmar Ltd., Wroclaw, Poland
A new method of symbolic analysis of large-scale networks is presented.
It is based on a terminal suppression procedure applied to the compacted
modified node admittance matrix. No circuit partitioning is required. Instead,
a locally optimal pivoting strategy minimises the number of symbolic operations.
The technique is conceptually simple and produces hierarchical formulae
of significantly lesser complexity than any exact method published to date.
Implementation Issues For Symbolic Sensitivity Analysis
Jeff Echtenkamp, Marwan Hassoun, Iowa State University, Ames, Iowa, USA
This paper discusses a hierarchical approach to sensitivity analysis, based
on the sequence of expressions method for circuit optimization applications.
This approach finds a minimal set of symbolic equations needed for symbolic
sensitivity analysis during the simulation phase. Results presented will
show that the cost of the sensitivity analysis can be minimal, compared
with other numeric methods.
Sequence of Expressions Generation Using Polynomial Reduction Method
Roman V. Dmytryshyn, Ukraine
This paper describes a transfer function sequence of expressions generation
technique in frequency or time domain for large circuits (50 nodes or more)
allowing symbolic representation for some or all elements. The symbolic
generator can be used for polyvariant analysis of linear or linearized networks,
which can consist of admittances, impedences and all four types of controlled
sources.
TA2.10 Antennas, Radar and RF Microwave Systems - Marian Kazimierczuk,
Chairperson - Scheman Room 171 - 179
Analysis of Harmonic Termination Impedance on RF/Microwave Multiplier
Efficiency
Donald G. Thomas, G.R. Branner, University of California, Davis, California,
USA
Harmonic terminating impedances have been shown to drastically effect the
performance of RF /Microwave frequency multipliers. In the literature, various
apparently differing conclusions have been obtained on the proper terminating
for active multipliers to achieve optimum performance. This paper presents
a rigorous and concise approach leading to the determination of proper harmonic
terminating impedances for optimum multiplier efficiency. This approach
is illustrated in this paper for HEMT frequency multipliers is S and C bands.
Excellent results have been obtained which have provided conversion gains
of 6 dB with harmonic suppression of greater than 25 dBc utilizing this
approach.
A Minuturized Lumped-Distributed Balun for Modern Wireless Communication
Systems
Suresh Prasad Ojha, G.R. Branner, B. P. Kumar, University of California,
Davis, California, USA
This paper describes the design of a compact hybrid balun circuit utilizing
distributed microstrip coupled lines and lumped capacitors. Extensive simulations
have been illustrated to show the effects and tradeoffs of changing important
design parameters, and performance-enhancing changes that led to the final
balun design, which gave excellent measured performance.
Design Formulae for a Class of Microstrip Tee Junction Power-Divider
Circuits
B.P. Kumar, G.R. Branner, D. James, University of California, Davis,
California, USA
This paper presents a method for accurate design of a class of narrow-band
and broad-band microstrip power-divider T junction circuits. The technique
is based on a set of design formulae, which were obtained from extensive
in-depth simulation and measured data obtained on several circuit designs
realized in the 1-8 Ghz frequency range.
A Linearized 1 GHz Class E Amplifier
G.D. Funk, Nortel, Calgary, Alberta, Canada; R.H. Johnston, University
of Calgary, Calgary, Alberta, Canada
An envelope elimination and restoration amplifier is analyzed, built and
tested at 1 GHz. The pre dicted amplifier performance closely matched the
measured amplifier performance. It is determined that a few key circuit
parameters largely control the amplifier intermodulation performance. It
is found that time delay matching of the phase signal information and the
envelope signal information is very important. It is also found that the
zero voltage signal feed through of the class E amplifier is also a a significant
parameter. The cascaded connection of the modulator and class E amplifier
with respect to the power flow from the supply to the rf signal output places
high demands on the modulator and amplifier efficiency.
New Techniques for Reflector Network Design In Single-Ended HEMT RF/Microwave
Frequency Multipliers
Donald G. Thomas, G. R. Branner, University of California, Davis, California,
USA
Microwave and RF frequency multipliers have a wide range of uses in the
electronic arena. It has been demonstrated that incorporating reflector
networks into the design process can improve the performance of multipliers.
This paper presents the development of alternative designs for reflector
networks used in the designing of HEMT frequency multipliers. Conversion
gains of 6.5 dB for narrowband designs (10% bandwidth) and 1 dB for wideband
designs (35% bandwidth) have been attained. The fundamental and third harmonic
rejection is approximately 30 dBc for the narrowband designs and 50 dBc
for the wideband designs.
Design of an Integrated Optical Receiver for a Phased Array Antenna
S.M. Frimel, T.E. Conklin, K.P. Roenker, R.R. Kunath, University of Cincinnati,
Cincinnati, Ohio, USA
This paper describes the design of the photodetector, HBT transistor and
preamplifier for a long wavelength (1300 nm), monolithically integrated
optical receiver for use in optical signal distribution of microwave signals
(6-13 GHz) for a phased array antenna.
Low Power Pipelined FFT Architecture for Synthetic Aperture Radar Signal
Processing
Bum Sik Kim, Lee-Sup Kim, Korea Advanced Institute of Science and Technology,
Seoul, Republic of Korea
A new FFT architecture for SAR (Synthetic Aperture Rader) signal processing
is presented. The proposed architecture adopts several new techniques for
low power operation and high throughput. Storage element and Delay Locked
Loop (DDL) are newly designed for constant geometry radix-4 pipelined DIF
FFT architecture. By simulations, it is verified that the proposed FFT architecture
enables 4096 point FFT operation in 336.04 msec by cascading six chips in
series.
Accuracy of Residual Phase Noise Characterization of Active RF/Microwave
Devices
Donald G. Thomas, G.R. Branner, University of California, Davis, California,
USA
Phase noise is widely recognized as a crucial parameter in many classes
of microwave communication systems. Phase noise can deteriorate the signal-to-noise
ratio and can cause severe problems in data fidelity in receiving systems.
A precise measurement of phase noise characteristics is significant in the
development of system architecture and component selection. The measurement
accuracy of phase noise tests can be seriously corrupted by the effects
of the bias supply of active devices being characterized for spectral density.
This paper presents an in-depth analysis of accuracy problems encountered
with such bias supply effects and provides quantitative solutions to these
problems.
Low Power Consumption Voltage Controlled Oscillator Design
David Q. Xu, G.R. Branner, B.P. Kumar, University of California, Davis,
California, USA
This paper illustrates the design and fabrication of a unique, compact and
low power consumption Voltage Controlled Oscillator (VCO) for wireless communication
applications. The device which was fabricated using lumped components on
a microstrip dielectric substrate, exhibited excellent circuit performance
for very low bias values of 1 V and 0.86 mA.
Reduced-Sized Low Noise-Low Power Consumption Amplifier Designs for Communications
and RF Applications
Aaron H. Ching, G.R. Branner, Donald G. Thomas, University of California,
Davis, California, USA
Low-noise amplifiers are extremely significant components in most RF cellular
and communications devices. While current design techniques achieve either
low noise or high gain, exclusively, little research has been done to reduce
their power consumption while simultaneously meeting both of the aforementioned
objectives. This paper presents important techniques for the design and
development of spatially compact amplifiers that simultaneously provide
low noise figure, high gain, low-power consumption, and low VSWR. The design
technique is illustrated by the realization of both distributed and discrete
circuits centered in the 1.8 GHz frequency range.
12:00 - 1:30 pm Awards Luncheon - Scheman Room 220 - 240
Giants Magnetoresistance - A Paradigm Shift for Magnetics
Dr. James Daughton, Nonvolatile Electronics, Inc. (see special guest
speakers, page 67)
1:30 - 3:30 pm CONCURRENT SESSIONS
TP1.1 Integrated Magnetoresistive Devices and Interface Circuits - William
Black, Chairperson - Scheman Room 167
The Design of Magnetoresistive Devices
Brenda Everitt, Nonvolatile Electronics Inc., Eden Prairie, Minnesota,
USA
Magnetoresistive devices exhibiting the conventional anisotropic-magnetoresistive-effect
(AMR) or the new giant-magnetoresistance effect (GMR) offer many possible
solution to both magnetic field sensing and non-volatile storage. The characteristics
of these devices will be described along with typical sensing strategies.
Micromagnetics in Small Size AMR and GMR Devices
Jian-Gang Zhu, University of Minnesota, St. Paul, Minnesota, USA
Magneto-electronic devices, such as magnetic random access memory (MRAM),
have generated
significant research interest in recent years. Micromagnetic properties
of these devices determine the performance characteristics as well as the
device stability and reliability. In this paper, microscopic magnetization
processes in small AMR and GMR devices are discussed with various examples
of device designs using advanced micromagnetic modeling analysis.
A Non-volatile 16k-bit MRAM Memory
Allan Hurst Jr., Honeywell Solid State Electronic Center
The design and experimental results from the first commercially viable 16k-bit
non-volatile RAM using magnetoresistive memory elements will be described.
The device allow unlimited read/write cycles and has a read-cycle time of
less the 250 nsec. A description of memory operation and various design
details will be described.
A Universal Low-Field Magnetic Field Sensor Using GMR Resistors on a
Semicustom Bi -CMOS Array
Jay Brown, Nonvolatile Electronics Inc., Eden Prairie, Minnesota, USA
A universal mixed-mode BiCMOS array has been combined with GMR resistors
and plated field magnifiers to achieve a sensitive easily reconfigurable
low-field magnetic sensor. The circuit may be configured for either analog
or digital outputs with full-scale ranges of as low as 5 Gauss and may be
used in applications of between 5 and 20 volts.
Integrated GMR Isolation Technique
William Black, Iowa State University, Ames, Iowa, USA; Ted Hermann, Nonvolatile
Electronics, Inc., Eden Prairie, Minnesota, USA; Wai-Leung Hui, Iowa State
University, Ames, Iowa, USA
An integrated isolation device has been realized which uses a magnetically
sensitive Giant Magnetoresistive Ratio (GMR) resistor in conjunction with
an isolated input current loop on the same die. This device has been demonstrated
in isolation circuits using conventional discrete components and packaged
integrated GMR isolators that display >1000 V of isolation protection
between input and output.
TP1.2 Design and Synthesis - Youssef Saab, Chairperson - Scheman
Room 262
Mapping CIRCAL Algorithms to Event Logic Using A Standard Cell Library
K.M. Elleithy, A.A. Amin, King Fahd University of Petroleum and Minerals,
Dhahran, Saudi Arabia
The work reported in this paper is part of a silicon compiler that receives
a parallel algorithm written in CIRCAL and produces a VLSI implementation.
The implementation logic used is the asynchronous event logic. A
generated netlist of event logic modules is used to produce the VLSI mask
layout geometries for this circuit using the standard cell approach. A standard
library of cells for event logic modules has been designed, simulated and
its layout generated.
An Efficient Gate Re-assignment Algorithm in Post Technology Mapping
Tzu-Hsi Pan, Chin-Long Wey, Michigan State University, East Lansing,
Michigan, USA
This paper presents an efficient gate transformation algorithm for logic
minimization under delay constraints. A mapped network, obtained from a
given logic optimizer and a cell library, is re-mapped to a virtual gate
library. A set of transformation is generated to transform the virtual cells
to real library cells under delay constraints. Results on MCNC benchmark
circuits show that the algorithm achieves a significant improvement in area
and speed.
Synthesis of Electrical Circuits Through Global Optimization
Stanislaw Osowski, Witold Debowski, Warsaw University of Technology,
Warsaw, Poland
The paper presents the application of the global optimization methods to
the synthesis of electrical circuits. Two kinds of approaches are investigated:
the multistart and simulated annealing methods. To accelerate the optimization
program the symbolic form of solution of electrical circuit has been developed
and applied in the software package. The gradient components are determined
using simplified approach taking benefits from the symbolic form of solution.
The program has been tested on many examples of different electrical circuits
and the results of numerical experiments are pre sented and discussed in
the paper.
Monotonic Iterations in RC Circuits
Corneliu A. Marinov, Cristian Budianu, Polytechnical University of Bucharest,
Bucharest, Romania This paper deals with iterative methods of relaxation
type used for solving linear RC circuits in dynamic and D.C. regime. One
proves that choosing the starting points in a specific and easily computable
manner, the algorithm provides tighter and tighter monotonic bounds of the
solution. The results are of interest in timing simulation of large MOS
circuits.
Synthesis of Current-Mode and Voltage-To-Current-Mode Circuits
Zbigniew Lata, Peter Aronhime, University of Louisville, Louisville,
Kentucky, USA
This paper describes methods of devising active Current-Mode and Voltage-Current-Mode
networks and improving the performance of existing active networks. The
circuits are synthesized by applica tion of dependent sources to a parent
network. The synthesis techniques provide indication of where in the original
network dependent generators should be introduced. An example of the application
of these techniques is given.
TP1.3 Controls and Stability - Degang Chen, Chairperson - Scheman
Room 260
Feedforward Control of PWM Buck Converters with Sawtooth Peak Value
Modulation
Marian K. Kazimierczuk, Mohammad Ali Izadi, Anotonio Massarini, Wrignt
State University, Dayton, Ohio, USA
A feedforward control circuit with a peak value voltage modulation of a
sawtooth generator has been analyzed for the PWM buck converter. A simple
theory for this circuit has been developed and experimentally tested. The
measured line regulation was less than 0.2\% per 1~V of the input voltage,
using the feedforward control only.
A Parallel Port Interface Circuit for Computer Control Applications Involving
Multiple Stepper Motors
Mike J. Johnson, Guru Subramanyam, University of Northern Iowa, Cedar
Falls, Iowa, USA
A parallel port interface circuit was designed, fabricated and tested for
programmed control of multiple stepper motors used in a robotic arm and
a linear position table. The interface circuit consisted of a tri-state
buffer driver, a decoder circuit, a phase sequencing circuit and a power
output circuit. A menu driven QBASIC program controlled the robotic arm
and the position table.
The Generalized State-Space Description of Positive Realness and Bounded
Realness
He-Sheng Wang, Fan-Ren Chang, National Taiwan University, Taipei, Taiwan,
R.O.C.
Positive realness and bounded realness are two important issues in system
theory. Some related applications about these notions include analysis and
synthesis of passive networks, optimal designs in control and estimation,
stability investigations in linear/nonlinear closed-loop systems; etc..
In this paper, we propose the equations of constant matrices, which are
stabilizable and detectable realiza tions of impulse-free generalized state-space
systems, to describe the positive real and bounded real properties. The
estabilished generalized positive real lemma and bounded real lemma are
necessary and sufficient. They are the extensions of results in [5], in
which the state-space realizations are considered. The impulse-free generalized
state-space systems contain both finite and nondynamic infinite modes. The
state-space systems contain finite modes only. To express those algebraic
restrictions among state variables is easier in the generalized state-space.
New Techniques for the Pole Placement of Singular System
Lee-Chuang Hsu, Fan-Ren Chang, National Taiwan University, Taipei, Taiwan,
R.O.C.
New techniques for pole placement problem of single input singular systems
are proposed in this paper. These techniques provide different ways to approach
the generalized Ackermann's formula with better numercial properties and
flexibility. Since the solution of the pole placement problem depend on
the singularity of the matrix E. Two sets of recursive algorithms are presented
separately corresponding to the matrix E is singular and nonsingular respectively.
These algorithms are verified and implemented in MATLAB program.
TP1.4 Adaptive Signal and Image Processing Theory and Applications -
M. Das, L. Udpa, Chairpersons
Hoda S. Abdel-Aty-Zohdy, M Das, Session Organizers - Scheman Room 252
A Comparative Study of System Identification Techniques for Modeling
of Time-Varying Signals and Systems
Thomas H. Hunt, Ford Motor Company, Dearborn, Michigan, USA
The modeling and identification of time-varying signals and systems is a
very important problem in adaptive signal processing and control. Although
a wide variety of system identification methods have been proposed to tackle
this problem, very little efforts have so far been made to compare their
relative performances. This paper makes an attempt to do that. The key contributions
of this paper are three fold; namely, i) determination of the behavior of
several recursive parameter estimation algorithms when they are modified
to accommodate time-varying signals/systems, ii) ranking of the above algorithms
according to their complexity, efficiency, robustness, convergence rate,
and ability
to cope with noisy signals, and iii) discussion of methods to select algorithm
design parameters. rate, and ability to cope with noisy signals, and iii)
discussion of methods to select algorithm design parameters.
A Novel Boundary Detection Algorithm Based on a Vector Image Model
N. Eua-Anant, L. Udpa, Iowa State University, Ames, Iowa, USA
Boundary detection algorithms are of interest in a number of disciplines
ranging from robotics and computer vision to remote sensing and nondestructive
evaluation. This paper presents a novel boundary detection algorithm based
on a model of a particle motion in a force field. The Hamiltonian and Lagrangian
gradients, derived from a vector edge field, are used as the tangential
and normal driving force fields and the boundary is extracted by estimating
the from a vector edge field, are used as the tangential and normal driving
force fields and the boundary is extracted by estimating the particle trajectory.
The algorithm is robust, computationally fast and offers subpixel accuracy.
The performance of the algorithm is demonstrated using images of high curvature,
low contrast and poor signal-to-noise-ratios.
Dynamic Stochastic Segmentation of On-Line Signature Contours
Mark J. Paulik, N. Mohankrishna, Michael Nikiforuk, University of Detroit
Mercy, Detroit, Michigan, USA
This paper presents a new on-line signature modeling approach for writer
identification and verifica tion. The method is based on the observation
that many on-line signature waveforms demonstrate sequential behavior, i.e.,
over short segments of the signal the statistical properties are relatively
consistent, and then the sequential behavior, i.e., over short segments
of the signal the statistical properties are relatively consistent, and
then the properties change abruptly or gradually to a different characterization.
Such a contour is, therefore, represented as an ordering of unique "curve
types", and modeled as a jump-stationary autoregressive (AR) process.
Next, a stochastic segmentation algorithm, which divides the signature contour
into parsimonious segmental AR models, is devel oped, and finally, the segmental
model is utilized to provide effective identification and authentication
results.
Detection of Jumps in Noisy Signals Using an Adaptive Stochastic Gradient
Method
Anthony Cooprider, Ford Motor Company, Dearborn, Michigan, USA; Manohar
Das, Oakland University, Rochester, Michigan, USA
This paper introduces a novel technique for the detection of jumps in noisy
signals using an adaptive stochastic gradient method. This method is an
improved and extended version of the conventional stochastic gradient (SG)
operator, which utilizes a FIR Wiener filter. The novel contributions in
this paper are two fold; namely, i) introduction of a robust method for
estimating signal autocorrelation coefficients, signal-to-noise-ratio and
noise variance, and ii) adaptation of the Wiener filter coefficients in
a block-by-block fashion. Improved performance of the proposed method over
conventional SG and filtered derivative techniques is demonstrated using
both synthetic and real data sets.
An Improved ASIC Design and Implementation for Color Space Conversion
Applications
Mahmoud Nsour, Hoda S. Abdel-Aty-Zohdy, Oakland University, Rochester,
Michigan, USA
The design and VLSI implementation of an ASIC chip, which performs real
time conversion, the Red, Green, and Blue (RGB) color coordinates to CIE
(Commission Internationale de l'Eclairage) standard L*(luminance), a*(redness-greenness),
and b*(yellowness-blueness) color coordinates, is presented. High-speed
operation is achieved by pipelining the input data, and performing parallel
operations. The ASIC is implemented using CMOS 2.0 um n-well process. It
occupies an area of 1.55 X 1.45 mm^2. The chip is intended to be used in
colorimetry manufacturing inspection and robotics preci sion. The available
silicon area and number of pads, in a tiny chip frame, limited the inputs
to 3 bits each. a* and b* are 7 bits each, L* is 6 bits. Propagation delay
of the prototypes is less than 100 ns.
Adaptive Cancellation of AM Radio Band Ignition Noise Interference in
the Automobile
Patrick J. Mills, N. Mohankrishnan, University of Detroit Mercy, Detroit,
Michigan, USA
The ignition circuit of an automobile is the source of a significant amount
of EMI that is picked up
on the AM radio band within the vehicle. Classical adaptive signal processing
solutions are used
to reduce the effects of this interference. The methods investigated are
demonstrated using actual signals acquired from an automobile.
Statistical Signal Modeling Techniques for Automated Recognition of Water-Borne
Micro bial Shapes
M. Das, F. Butterworth, R. Das, Oakland University, Rochester, Michigan,
USA
Till this date, researchers have devoted very little attention to the problem
of automated detection and identification of water-borne microbiota (bacteria,
algae, and protozoa), although this field stands to gain tremendously from
recent advances made in signal processing and pattern recognition techniques.
This paper describes some preliminary results obtained from our on-going
efforts in signal processing and pattern recognition techniques. This paper
describes some preliminary results obtained from our on-going efforts to
address the above problem. The topics addressed include acquisition and
creation of a microbiota image database, enhancement using Wiener/nonlinear
filters, statistical modeling of shape contours, and classification. The
test results obtained from six different microbiota shapes are presented.
TP1.5 Adaptive Filters - John Doherty, Chairperson - Scheman Room
275
One-Dimensional Block Adaptive IIR Filters
Alfredo C. Tan, Fairleigh Dickinson University, Teaneck, New Jersey,
USA
We present the block implementation of adaptive infinite impulse response
filters based on least -mean-square algorithm and output-error formulation.
This approach leads to a reduction in overall computational complexity and
to a fast implementation involving parallel processors or serial proces
sors and fast Fourier transform techniques. Computer simulations are also
provided to demonstrate the practical applications of the proposed adaptive
filters.
Comparison of Microprocessor-based and FPGA-based Adaptive Sample Rate
Notch Filters
Richard H. Strandberg, Prayag B. Patel, Michael A. Soderstrand, University
of California, Davis, California, USA
Adaptive sample rate filtering is an effective, hardware-efficient method
of removing narrowband interference from broadband communication signals.
AMD 29200 microcontroller and Xilinx XC4010 FPGA implementations are presented.
Although intended for communication applications, the systems are demonstrated
using an audio signal as the broadband signal and sinusoidal interference
is introduced and eliminated.
A New Two-Dimensional Parallel Block Adaptive Filter
Shigenori Kinjo, Hiroshi Ochi, University of the Ryukyus, Ikinawa, Japan;
Hitoshi Kiya, Tokyo Metropolitan University, Tokyo, Japan
Two-dimensional (2-D) adaptive digital filters (ADF's) for 2-D signal processing
have become an fascinating area of the adaptive signal processing. However,
conventional 2-D FIR ADF's require many coefficients. For example, the TDLMS
requires NxN multiplications per pixel. We propose a new 2-D adaptive filter
using the 2-D FFT's. The proposed adaptive filter has parallel structure
and we can reduce the computational complexity to O(logN) per pixel.
On DSP Implementation of Adaptive IIR Filters
J.E. Cousseau, P.D. Donate, Universidad Nacional del Sur, Bah'a Blanca,
Argentina; P.S.R. Diniz, COPPE/EE/Federal University of Rio de Janeiro,
R.J., Brasil
Some real-time DSP experiments with adaptive IIR filters are addressed in
this paper. The perfor mance comparisons involve the LMSEE, the BRLE and
the QCEE algorithms. A discussion of the main characteristics of each algorithm
is included. Some aspects of the implementation involving
the updating algorithm, the normalization, the quantization strategy and
the internal scaling are discussed. Preliminary results show that finite
wordlength effects are more disturbing in the BRLE algorithm than in the
QCEE algorithm.
A Combined Direct and Variable Structure Method for Adaptive Filter
C.A. Busada, O. Orqueda, M.A. Jordan, Consejo Nacional de Investigaciones
Cientificas y Tecnicas, Argentina; A.C. Desages, Comision de Investigaciones
Cientificas de la Prov. de Buenos Aires, Argentina
This paper presents a new approach for adaptive control and signal filtering
with robust characteris tics that is based on model reference adaptive systems
and variable structure methods. An adaptive law is suggested that is able
to improve transient behaviors of the system particularly in cases when
external bounded perturbations acts on the system and time-varying plant
parameters are present.
TP1.6 Analog Filters II - Laurence Huelsman, Chairperson - Scheman
Room 250
Translinear Transconductor Design for Cochlear Filter Banks
Paul M. Furth, New Mexico State University, Las Cruces, New Mexico, USA;
Andreas G. Andreou, The Johns Hopkins University, Baltimore, Maryland, USA
The five major requirements of a transconductance-C integrator for use in
cochlear filter banks are: low voltage, low power, small area, wide tuning
range, and high dynamic range. The BiCMOS transconductor of Andreou and
Liu (1993), which incorporates MOSTs operating in strong and weak inversion
and a bipolar current multiplier, simultaneously satisfies all of these
design criteria. Moreover, each stage of the transconductor can be optimized
in order to achieve the best overall performance. A similar design strategy
can be applied to MOSFET-C implementations.
Low-Voltage CMOS GM-C Filter with Rail-To-Rail Common-Mode Voltage
Chung-Chih Hung, Kari Halonen, Veikko Porra, Mohammed Ismail, Helsinki
University of Technology, Espoo, Finland
In this paper, a CMOS design of low-voltage 5th-order elliptic low-pass
GM-C filter with rail-to-rail common-mode input voltage is introduced. The
OTA inside this filter is a low-voltage rail-to-rail voltage-to-current
converter. For the V-I converter, an N-type V-I converter cell is connected
in parallel with its counterpart, a P-type V-I converter cell, to achieve
common-mode rail-to-rail operation. Maximum-current selecting circuits are
utilized to generate constant-gm output currents for the OTA.
OTA-C Filters with Finite Zeros and Without Floating Capacitors
Luiz Caloba, Federico Galvez-Durand, Antonio C.M. de Queiroz, COPPE/EE/UFRJ,
Rio de Janeiro, Brazil
In this paper we present a novel technique for OTA-C filter realizations
with finite zeros based on doubly loaded passive ladder networks. Only grounded
capacitors are needed; all floating capacitors are replaced with active
simulations eliminating bottom-plate parasitic capacitors and non-observable
poles. Bandpass, highpass and bandstop filters are easily obtained from
a lowpass OTA-C prototype applying standard frequency transformations that
preserve the active simulation of floating capaci tors, i.e., the finite
zeros realization. Also, some stability problems of highpass and bandstop
filters are briefly addressed.
Novel Structure of Signal Flow Graph for OTA-C High-Pass Filters
Maciej Guzinski, Technical University of Gdansk, Gdansk, Poland
In this paper, a structure of signal flow graph for OTA-C high-pass filters
is presented. The structure of the graph is similar to the ones of low-pass
and band-pass filters. Realization of the graph in OTA-C is an integrator-based
and the proposed graph could be more easily implemented as an electronic
circuit than other graphs. Unfortunately, the design involves some floating
capacitors instead of the grounded ones.
Versatile Second Order Filter Structures for Low-Voltage Multiple-Input
Amplifiers
Nabil I. Khachab, Abdulaziz Al-Saquer, Joji George Varghese, Kuwait University,
Safat, Kuwait
Two versatile second order filter architectures have been presented with
applications to double and single ended multiple input amplifier configurations,
on which tests were performed for B/P, H/P, L/P and notch filter realizations.
The Gm tunability of the fully-complementary, Composite Folded Cascode (CFC)
based amplifier test structures is brought about by a MOSR scheme with center
-frequency variations in the upper Mega hertz range, using power supplies
of +2.5V.
TP1.7 Nonlinear Analysis of Power Electronic Systems - Pallab Midya,
Chairperson - Scheman Room 208
Optimal Energy Management for Solar Car Race
Graham S. Wright, University of Illinois at U-C, Urbana, Illinois, USA
This paper describes a solar car simulation and race strategy program
developed for the University of Illinois Sunrayce '95 solar car race team.
The strategy problem can be well posed as a global time -minimization problem
over the entire race. This article discusses the algorithms used some of
our strategic insights and expectations prior to the race, and how our battle
plans fared in contact with
the enemy.
Continuous-Time Optimization of Gate Timing for Synchronous Recertification
Jonathan Kimball, Philip T. Krein, University of Illinois at U-C, Urbana,
Illinois, USA
Recent advances in electronics call for higher efficiency, lower output
voltage power converters.
On method proposed is to use synchronous converters, which use two controlled
switches (MOSFETs). A new algorithm is shown for adjusting the relative
timing of the gate signals to mini mize input current, and therefore input
power, for a fixed output. This is shown to be a member
of a more general family of analogy auto-tuning algorithms. Implementation
details and experimental results follow.
sessions August 20 Tuesday
Efficiency Analysis of Switched Capacitor Doubler
Pallab Midya, Motorola Chicago Corporate Research Laboratory, Chicago,
Illinois, USA
Switched capacitors doubler and triplers are used to step-up dc voltage.
They are readily integrable which makes them a good choice for numerous
applications. Their power conversion efficiency is limited due to switch
drops, parasitic capacitances and resistances. However, their efficiency
is also inherently limited by the circuit topology. This paper provides
an upper bound for the power conver sion efficiency of a doubler assuming
ideal components. This analysis also provides design guidlines, in terms
of capacitor size and switching frequency, for meeting efficiency goals.
Finally, an alternate circuit topology is posed that would not have this
efficiency bound.
An Improved Steady-State Method Applying Broyden's Technique to the Shooting
Method
Uma Ekambaram, Resve Saleh, University of Illinois at U-C, Urbana, Illinois,
USA
This paper presents an efficient steady-state analysis method applicable
to converter circuits.
The solution technique is based upon the shooting method. This method poses
the steady state problem as a boundary value problem by equating the states
at the beginning and end of a time period. The equation that needs to be
solved is a nonlinear equation in the state transition function. Previously
this equation was solved using Newton's method. The new technique uses Broyden's
method to solve this equation. This is faster, requires significantly less
matrix computation and is capable of handling circuits which have internally
and/or externally controlled switches such as power converters, without
necessarily taking switching time variations into consideration.
Small Signal Analysis of PWM Voltage Mode and Current Mode Control
Pallab Midya, Motorola Chicago Corporate Research Laboratory, Chicago,
Illinois, USA
Small signal analysis is commonly used in switched converter design. The
PWM (pulse width modu lation) block is usually approximated with a single
pole response. The PWM block is a nonlinear block that interacts with the
control loop and is not accurately represented by this model. In this paper
a time averaged analysis is presented that computes the response of the
PWM block in Voltage Mode and Current Mode control. This analysis models
the PWM block with the control loop and comes up with a gain and delay model.
This analysis also yields qualitative data on the relative performance of
voltage and current mode controls.
TP1.8 Next Generation Optical Networks Based on Wavelength Division
Srini Trindandapani, Chairperson - Scheman Room 204
Adaptive Routing Algorithms for Wavelength-Routed All-Optical Networks
Ahmed Mokhtar, Murat Azizoglu, University of Washington, Seattle, Washington,
USA
This paper considers routing and wavelength assignment in wavelength-routed,
all-optical networks. Algorithms are proposed for adaptive routing of connection
requests, which take into account the adaptive routing of connection requests,
which take into account the current network state in an attempt to minimize
the call blocking probability. Analytical and simulation results are obtained
for comparative performance evaluating, and complexity issues are addressed.
Towards Passive Wavelength-Routed Optical Networks
Dhritiman Banerjee, Biswanath Mukherjee, University of California, Davis,
California, USA
We explore an optical network architecture which employs dense WDM technology
and passive Waveguide Grating Routers (WGRs) to establish a virtual topology
based on lightpaths. We examine the motivation and the technical challenges
involved in this approach, propose a network design algorithm, and provide
some illustrative performance results.
Wavelength Routers in WDM Local Area Networks
Michael S. Borella, Depaul University, Chicago, Illinois, USA; Jason
P. Jue, University of California, Davis, California
This paper presents a novel scheme for scheduling packet traffic on a wavelength-division-multi
plexed (WDM) local optical network which employs a wavelength router. An
N-port latin router
allows N^2 times N^2 connectivity via only N physical wavelengths. We propose
TDM schedules
for interconnecting MN nodes with a wavelength router. We show that for
non-zero transceiver tuning time, throughput on the order of N can be achieved.
Channel-Sharing in Local Optical Networks
Srini Trindandapani, Iowa State University, Ames, Iowa, USA
We develop channel-sharing techniques in wavelength-division-multiplexed
(WDM), multi-channel,
sessions August 20 Tuesday
multi-hop systems based on the technological limitation that the number
of channels, w, is less than the number of nodes, N, in the system. We show
that having w<N channels is actually desirable from the delay-performance
point of view. We obtain estimates for the optimal number of channels which
minimizes the average delay in the network.
Device/Perfomance Trade-Offs in All-Optical Networks
Richard A. Barry, MIT Lincoln Laboratory, Lexington, Massachusetts, USA
This talk will focus on the benefits of using different classes of optical
and electro-optic devices
for circuit switched all-optical WDM networks. Two scenarios are considered:
passive LANs or MANs which contain only passive optical devices, and configurable
WANs which contain many all-optical switching nodes connected in a nmesh
topology.
On WDM-ATM Network Architecture
Krishna M Sivalingam, University of North Carolina-Greensboro, Greensboro,
North Carolina, USA
The objective of the paper is to propose a hierarchical network architecture
based on all-optical Wavelength Division Multiplexed (WDM) networks extended
(for longer distances) through Asynchro nous Transfer Mode (ATM) networks.
The local subnetworks are designed as all-optical WDM net works that require
tunable components and a media access protocol. The WDM networks will be
interconnected using generalized multichannel ATM switches that utilize
multiple wavelengths
on the input/output links.
TP1.9 VLSI in Satellite Communications - Mohsin Jamali, Chairperson -
Scheman Room 299
Transmit Pulse Shaping Filters and CORDIC Algorithm Based Precompensation
Mark J. Vanderaar, Dale L. Mortensen, Ronald L. Bexten, NYMA, Inc.
The design and architectural implementation of low complexity pulse shaping
filters and algorithmic precompensation for satellite communications transmitters
is presented. A lookup table (LUT) approach is used to implement the pulse
shaping that provides good spectral efficiency with low implementation loss.
A Coordinate Rotation DIgital Computer (CORDIC) algorithm technique is use
to implement the precompensation, resulting in a reduction of the deleterious
effects of channel nonlinearities. An architecture for adaptive precompensation
is also presented. Issues including number representation, BER performance,
and Field Programmable Gate Arrays (FPGAs) complexity are discussed. Emphasis
is placed on low complexity techniques to enable throughput rates in the
tens of megabits per second using today's FPGAs.
Error Coding and Loss Cell Recovery in Asynchronous Transfer Mode
W.W. Wu, M.U. Wu, J. Budinger, H. Kim, The Consultare Technology Group,
Inc., Bethesda, Maryland, USA
Rad-Tolerand Flight VLSI From Commercial Foundries
Jody Gambles, Gary K. Maki, University of New Mexico, Albuquerque, New
Mexico, USA
A Compact Cell Design for a Multiport Register File
Zhi Li, E.D. Smith, S.C. Kwatra, The University of Toledo, Toledo, Ohio,
USA
VLSI Implementation of On Board Processing Subsystems for Satellite
Channels
M.M. Jamali, S.C. Kwatra, The University of Toledo, Toledo, Ohio, USA
A High Speed Array Architecture for 2D Wavelet Transforms
Magdy Bayoumi, The University of Southwestern Louisiana, Lafayette, Louisiana,
USA
TP1.10 DSP Architectures and Implementations - Lalita Udpa, Chairperson
- Scheman Room 171 - 179
Micro-Controlled - MIDI - In-line Transposer
D. Kaur, Don George, The University of Toledo, Toledo, Ohio, USA
sessions August 20 Tuesday
A Unified View of CORDIC Processor Design
Shaoyun Wang, Crystal Semiconductor Corporation, Austin, Texas; Vincenzo
Piuri, Politecnico
di Milano, Milano, Italy; Earl E. Swartzlander Jr., The University of Texas
at Austin, Austin, Texas, USA
A unified view of architectures proposed in literatures is presented. The
paper provides a wide spectrum of architectures, a coordinated and comprehensive
design methodology, main figures
of merit characterizing architectures' performance and complexity, and design
guidelines for optimal designes with respect to requirements and constraints
of a specific application.
A Class of Parallel Architectures for Fast Fourier Transform
Chi-Hsiang Yeh, Behrooz Parhami, University of California, Santa Barbara,
California, USA
We propose a new class of parallel architectures called unfolded swapped
networks (USN) for Fast Fourier Transform (FFT) and related problems. N-point
FFT can be executed on a USN faster than
on a butterfly network by a factor of Theta(log N), assuming that the routing
delay is proportional to the logarithm of the length of a link. USNs can
be constructed with small butterfly (or any other FFT computation) modules,
each built on a chip, and requires pins considerably fewer than a similar-sized
butterfly network.
Implementation of a Digital Amplitude Detector Based on the CORDIC Transform
Jan Codenie, Ziaohua Wang, Xingzhi Qiu, Jan Vlietinck, Jan Vandewege,
Peter Lambrecht, Univer sity of Gent, Gent, Belgium
A digital implementation of an amplitude detector for Automatic Gain Control
in a complex modula tion format receiver is presented. The algorithm is
based on the Co-Ordinate Rotation Digital Com puter method which makes the
amplitude detection very fast and accurate. The efficient topology enables
realisation in a standard programmable gate array. Measurements on a 16QAM
burst mode receiver are presented.
A Parallel Pipelined DSP Processing Core
V.C. Aikens II, J.G. Delgado-Frias, Binghamton University, Binghamton,
New York, USA;
G.G. Pechanek, IBM Corp., Microelectronics Division, NC, USA; S. Vassiliadis,
Delft University
of Technology, The Netherlands
Algorithms associated with Digital Signal Processing (DSP) are inherently
parallel. We propose
a novel architecture which operates in a parallel pipelined fashion. We
show the proposed architec ture is well suited for algorithms used in DSP,
as well as compression of full-motion video for
compliance with the MPEG-2 standard.
A Reconfigurable Processing System for DSP Applications
G. Knittel, University of Tuebingen, Tuebingen, Germany
A small-scale, reconfigurable processing system is presented. It contains
four FPGAs (9K to 13K gate equivalents), 2MByte Flash Memory, 256KByte fast
SRAM and a 16-bit MAC unit. The system has
a PCI-bus interface and was designed to speed up DSP, image processing and
computer-graphics algorithms. Examples from medical imaging are shown.
An Integrated Software Platform for the Design and DSP-Based Implementation
of Digital Filters
Mario Sarcinelli Filho, Hansjorg Andreas Schneebeli, Arnaldo Cordeiro
Machado, Universidade Federaldo Esprito Santo, Vitoria, E.S., Brazil
This paper describes a software platform developed in order to support the
design and DSP-based implementation of digital filters. It is a WINDOWS
program designed to run on a personal computer containing a DSP board. A
card based on the 16-bit fixed point Texas Instruments TMS320C25 chip
is used, which is attached to the ISA PC bus. The developed software is
specially designed to accom plish three main features: the filter design
task, restricted to the PC microprocessor, the real-time synchronous filter
algorithm, running exclusively on the DSP, and the necessary information
exchang ing between both processors, in order either to load filter parameters
or to check for the filter input /output signals. In addition, the user
may edit/view text files containing the filter transfer function
or network coefficients, or edit/compile/debug files that contain assembly
code for the DSP.
DSPDEMO-Programming Package for Digital Signal Processing Learning
Gordana Jovanovic-Dolecek, Instituto Nacional de Astrofisica, Optica
y Electronica, INAOE, Puebla, Pue., Mexico
This paper presents the software package which is intended for the learning
of the fundamentals
of the digital signal processing. Both, the time domain and the frequency
domain representations
are given. Besides the deterministic signals, some demonstrations of a random
discrete-time signals,
sessions August 21 Wednesday
sessions August 21 Wednesday
are given too. The package is developed in MATLAB, and has been conceived
in the form of the functional files, each presenting one demonstration.
CMOS Implementation of a Fractionally Spaced Godard Equalizer
Sebnem Bora, Ali Berk Bora, Ramakrishna Nunna, Stevens Institute of Technology,
Hoboken,
New Jersey, USA
In this paper, we describe an efficient implementation of an architecture
for Blind Channel Equaliza tion. The cost function known as Goddard Cost
Function is minimized by using stochastic gradient descent algorithm. The
output of the architecture can be used as a real time equalizer and can
totally remove linear distortion appearing due to the imperfections of a
channel. Due to the dynamic adjusting of the step size, divergence is avoided.
The implementation optimizes on the number
of multiplications used.
5:00 - 10:00 pm Symposium Banquet at Living History Farms, Des Moines,
Iowa
(see particulars section for more information)